From 9dd6fcd9ece4433229181241bdaba9b2d0baa232 Mon Sep 17 00:00:00 2001
From: Kenneth Graunke <kenneth@whitecape.org>
Date: Wed, 3 May 2023 02:05:16 -0700
Subject: [PATCH] intel/compiler: UNDEF SubgroupInvocation's register

This value takes a few instructions to create, involving expanding
V-immediates, adding 8 for SIMD16, and so on.  We can mark it UNDEF
so that it's clear that although these are partial writes, we are
actually defining the entire value.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22835>
---
 src/intel/compiler/brw_fs_nir.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index dd7205b506a..f13adf5c5d4 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -282,6 +282,7 @@ fs_visitor::nir_emit_system_values()
       const fs_builder abld = bld.annotate("gl_SubgroupInvocation", NULL);
       fs_reg &reg = nir_system_values[SYSTEM_VALUE_SUBGROUP_INVOCATION];
       reg = abld.vgrf(BRW_REGISTER_TYPE_UW);
+      abld.UNDEF(reg);
 
       const fs_builder allbld8 = abld.group(8, 0).exec_all();
       allbld8.MOV(reg, brw_imm_v(0x76543210));