diff --git a/src/gallium/drivers/radeonsi/radeon_vcn_enc.c b/src/gallium/drivers/radeonsi/radeon_vcn_enc.c
index f4fb0d338b2..c57d9cd3e82 100644
--- a/src/gallium/drivers/radeonsi/radeon_vcn_enc.c
+++ b/src/gallium/drivers/radeonsi/radeon_vcn_enc.c
@@ -90,8 +90,8 @@ static uint32_t radeon_vcn_enc_blocks_in_frame(struct radeon_encoder *enc,
    bool is_h264 = u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC;
    uint32_t block_length = is_h264 ? PIPE_H264_MB_SIZE : PIPE_H265_ENC_CTB_SIZE;
 
-   *width_in_block  = PIPE_ALIGN_IN_BLOCK_SIZE(enc->base.width,  block_length);
-   *height_in_block = PIPE_ALIGN_IN_BLOCK_SIZE(enc->base.height, block_length);
+   *width_in_block  = DIV_ROUND_UP(enc->base.width,  block_length);
+   *height_in_block = DIV_ROUND_UP(enc->base.height, block_length);
 
    return block_length;
 }
@@ -391,8 +391,8 @@ static void radeon_vcn_enc_h264_get_slice_ctrl_param(struct radeon_encoder *enc,
    uint32_t num_mbs_total, num_mbs_in_slice;
 
    num_mbs_total =
-      PIPE_ALIGN_IN_BLOCK_SIZE(enc->base.width, PIPE_H264_MB_SIZE) *
-      PIPE_ALIGN_IN_BLOCK_SIZE(enc->base.height, PIPE_H264_MB_SIZE);
+      DIV_ROUND_UP(enc->base.width, PIPE_H264_MB_SIZE) *
+      DIV_ROUND_UP(enc->base.height, PIPE_H264_MB_SIZE);
 
    if (pic->num_slice_descriptors <= 1) {
       num_mbs_in_slice = num_mbs_total;
@@ -749,8 +749,8 @@ static void radeon_vcn_enc_hevc_get_slice_ctrl_param(struct radeon_encoder *enc,
    uint32_t num_ctbs_total, num_ctbs_in_slice;
 
    num_ctbs_total =
-      PIPE_ALIGN_IN_BLOCK_SIZE(pic->seq.pic_width_in_luma_samples, PIPE_H265_ENC_CTB_SIZE) *
-      PIPE_ALIGN_IN_BLOCK_SIZE(pic->seq.pic_height_in_luma_samples, PIPE_H265_ENC_CTB_SIZE);
+      DIV_ROUND_UP(pic->seq.pic_width_in_luma_samples, PIPE_H265_ENC_CTB_SIZE) *
+      DIV_ROUND_UP(pic->seq.pic_height_in_luma_samples, PIPE_H265_ENC_CTB_SIZE);
 
    if (pic->num_slice_descriptors <= 1) {
       num_ctbs_in_slice = num_ctbs_total;
diff --git a/src/gallium/drivers/radeonsi/radeon_vcn_enc.h b/src/gallium/drivers/radeonsi/radeon_vcn_enc.h
index 2cda3bcadcc..d756aefb443 100644
--- a/src/gallium/drivers/radeonsi/radeon_vcn_enc.h
+++ b/src/gallium/drivers/radeonsi/radeon_vcn_enc.h
@@ -15,8 +15,6 @@
 
 #include "ac_vcn_enc.h"
 
-#define PIPE_ALIGN_IN_BLOCK_SIZE(value, alignment) DIV_ROUND_UP(value, alignment)
-
 #define RADEON_ENC_CS(value) (enc->cs.current.buf[enc->cs.current.cdw++] = (value))
 #define RADEON_ENC_BEGIN(cmd)                                                                    \
    {                                                                                             \
diff --git a/src/gallium/drivers/radeonsi/radeon_vcn_enc_4_0.c b/src/gallium/drivers/radeonsi/radeon_vcn_enc_4_0.c
index 58baa06bc19..22dd3234841 100644
--- a/src/gallium/drivers/radeonsi/radeon_vcn_enc_4_0.c
+++ b/src/gallium/drivers/radeonsi/radeon_vcn_enc_4_0.c
@@ -96,10 +96,10 @@ static void radeon_enc_spec_misc_av1(struct radeon_encoder *enc)
    uint32_t min_log2_tiles_width_in_sb;
    uint32_t min_log2_tiles;
 
-   frame_width_in_sb = PIPE_ALIGN_IN_BLOCK_SIZE(enc->enc_pic.session_init.aligned_picture_width,
-                                       PIPE_AV1_ENC_SB_SIZE);
-   frame_height_in_sb = PIPE_ALIGN_IN_BLOCK_SIZE(enc->enc_pic.session_init.aligned_picture_height,
-                                       PIPE_AV1_ENC_SB_SIZE);
+   frame_width_in_sb = DIV_ROUND_UP(enc->enc_pic.session_init.aligned_picture_width,
+                                    PIPE_AV1_ENC_SB_SIZE);
+   frame_height_in_sb = DIV_ROUND_UP(enc->enc_pic.session_init.aligned_picture_height,
+                                    PIPE_AV1_ENC_SB_SIZE);
    num_tiles_cols = (frame_width_in_sb > max_tile_width_in_sb) ? 2 : 1;
    num_tiles_rows = CLAMP(p_config->num_tile_rows,
                          1, RENCODE_AV1_TILE_CONFIG_MAX_NUM_ROWS);