diff --git a/src/amd/common/nir/ac_nir.h b/src/amd/common/nir/ac_nir.h index bf10aca9cc8..639187f36fe 100644 --- a/src/amd/common/nir/ac_nir.h +++ b/src/amd/common/nir/ac_nir.h @@ -97,11 +97,16 @@ typedef struct { /* Generic per-patch slots. */ uint32_t vram_patch_output_mask; uint32_t lds_patch_output_mask; + + /* The highest index returned by map_io + 1. */ + uint8_t highest_remapped_vram_output; + uint8_t highest_remapped_vram_patch_output; } ac_nir_tess_io_info; void ac_nir_get_tess_io_info(const nir_shader *tcs, const nir_tcs_info *tcs_info, uint64_t tes_inputs_read, - uint32_t tes_patch_inputs_read, ac_nir_tess_io_info *io_info); + uint32_t tes_patch_inputs_read, ac_nir_map_io_driver_location map_io, + bool remapped_outputs_include_tess_levels, ac_nir_tess_io_info *io_info); bool ac_nir_lower_ls_outputs_to_mem(nir_shader *ls, @@ -134,8 +139,8 @@ void ac_nir_compute_tess_wg_info(const struct radeon_info *info, const ac_nir_tess_io_info *io_info, unsigned tcs_vertices_out, unsigned wave_size, bool tess_uses_primid, unsigned num_tcs_input_cp, unsigned lds_input_vertex_size, - unsigned num_mem_tcs_outputs, unsigned num_mem_tcs_patch_outputs, - unsigned *num_patches_per_wg, unsigned *hw_lds_size); + unsigned num_remapped_tess_level_outputs, unsigned *num_patches_per_wg, + unsigned *hw_lds_size); bool ac_nir_lower_es_outputs_to_mem(nir_shader *shader, diff --git a/src/amd/common/nir/ac_nir_lower_tess_io_to_mem.c b/src/amd/common/nir/ac_nir_lower_tess_io_to_mem.c index f115c67fa71..694ec55a5a8 100644 --- a/src/amd/common/nir/ac_nir_lower_tess_io_to_mem.c +++ b/src/amd/common/nir/ac_nir_lower_tess_io_to_mem.c @@ -169,11 +169,16 @@ typedef struct { void ac_nir_get_tess_io_info(const nir_shader *tcs, const nir_tcs_info *tcs_info, uint64_t tes_inputs_read, - uint32_t tes_patch_inputs_read, ac_nir_tess_io_info *io_info) + uint32_t tes_patch_inputs_read, ac_nir_map_io_driver_location map_io, + bool remapped_outputs_include_tess_levels, ac_nir_tess_io_info *io_info) { io_info->vram_output_mask = tcs->info.tess.tcs_outputs_read_by_tes & tes_inputs_read; io_info->vram_patch_output_mask = tcs->info.tess.tcs_patch_outputs_read_by_tes & tes_patch_inputs_read; + /* These shouldn't occur in TCS. */ + io_info->vram_output_mask &= ~(VARYING_BIT_LAYER | VARYING_BIT_VIEWPORT | + VARYING_BIT_PRIMITIVE_ID | VARYING_BIT_PRIMITIVE_SHADING_RATE); + io_info->lds_output_mask = (((tcs->info.outputs_read & tcs->info.outputs_written) | tcs->info.tess.tcs_cross_invocation_outputs_written | tcs->info.outputs_written_indirectly) & ~TESS_LVL_MASK) | @@ -183,6 +188,36 @@ ac_nir_get_tess_io_info(const nir_shader *tcs, const nir_tcs_info *tcs_info, uin io_info->vgpr_output_mask = (tcs->info.outputs_written & ~(tcs->info.tess.tcs_cross_invocation_outputs_written | tcs->info.outputs_written_indirectly) & ~TESS_LVL_MASK); + + io_info->highest_remapped_vram_output = 0; + io_info->highest_remapped_vram_patch_output = 0; + + if (map_io) { + u_foreach_bit64(i, io_info->vram_output_mask & ~TESS_LVL_MASK) { + unsigned index = map_io(i); + io_info->highest_remapped_vram_output = MAX2(io_info->highest_remapped_vram_output, index + 1); + } + + u_foreach_bit(i, io_info->vram_patch_output_mask) { + unsigned index = map_io(VARYING_SLOT_PATCH0 + i); + io_info->highest_remapped_vram_patch_output = MAX2(io_info->highest_remapped_vram_patch_output, index + 1); + } + + if (remapped_outputs_include_tess_levels) { + u_foreach_bit64(i, io_info->vram_output_mask & TESS_LVL_MASK) { + unsigned index = map_io(i); + io_info->highest_remapped_vram_patch_output = MAX2(io_info->highest_remapped_vram_patch_output, index + 1); + } + } + } else { + io_info->highest_remapped_vram_output = util_bitcount64(io_info->vram_output_mask & ~TESS_LVL_MASK); + io_info->highest_remapped_vram_patch_output = util_bitcount(io_info->vram_patch_output_mask); + + if (remapped_outputs_include_tess_levels) { + io_info->highest_remapped_vram_patch_output += + util_bitcount64(io_info->vram_output_mask & TESS_LVL_MASK); + } + } } static uint64_t @@ -1498,8 +1533,8 @@ void ac_nir_compute_tess_wg_info(const struct radeon_info *info, const ac_nir_tess_io_info *io_info, unsigned tcs_vertices_out, unsigned wave_size, bool tess_uses_primid, unsigned num_tcs_input_cp, unsigned lds_input_vertex_size, - unsigned num_mem_tcs_outputs, unsigned num_mem_tcs_patch_outputs, - unsigned *num_patches_per_wg, unsigned *hw_lds_size) + unsigned num_remapped_tess_level_outputs, unsigned *num_patches_per_wg, + unsigned *hw_lds_size) { unsigned num_tcs_output_cp = tcs_vertices_out; unsigned lds_output_vertex_size = util_bitcount64(io_info->lds_output_mask & ~TESS_LVL_MASK) * 16; @@ -1510,7 +1545,9 @@ ac_nir_compute_tess_wg_info(const struct radeon_info *info, const ac_nir_tess_io num_tcs_output_cp * lds_output_vertex_size + lds_perpatch_output_patch_size; unsigned num_patches = ac_compute_num_tess_patches(info, num_tcs_input_cp, num_tcs_output_cp, - num_mem_tcs_outputs, num_mem_tcs_patch_outputs, + io_info->highest_remapped_vram_output, + MAX2(io_info->highest_remapped_vram_patch_output, + num_remapped_tess_level_outputs), lds_per_patch, wave_size, tess_uses_primid); unsigned lds_size = lds_per_patch * num_patches + AC_TESS_LEVEL_VOTE_LDS_BYTES; diff --git a/src/amd/vulkan/nir/radv_nir_lower_abi.c b/src/amd/vulkan/nir/radv_nir_lower_abi.c index f8880face78..5508fe70bc9 100644 --- a/src/amd/vulkan/nir/radv_nir_lower_abi.c +++ b/src/amd/vulkan/nir/radv_nir_lower_abi.c @@ -260,7 +260,7 @@ lower_abi_instr(nir_builder *b, nir_intrinsic_instr *intrin, void *state) nir_def *num_tcs_mem_outputs; if (stage == MESA_SHADER_TESS_CTRL) { - num_tcs_mem_outputs = nir_imm_int(b, s->info->tcs.num_linked_outputs); + num_tcs_mem_outputs = nir_imm_int(b, s->info->tcs.io_info.highest_remapped_vram_output); } else if (s->info->inputs_linked) { num_tcs_mem_outputs = nir_imm_int(b, s->info->tes.num_linked_inputs); } else { diff --git a/src/amd/vulkan/nir/radv_nir_lower_io.c b/src/amd/vulkan/nir/radv_nir_lower_io.c index 2a32efad0fa..f0e1c5121a5 100644 --- a/src/amd/vulkan/nir/radv_nir_lower_io.c +++ b/src/amd/vulkan/nir/radv_nir_lower_io.c @@ -243,8 +243,8 @@ radv_nir_lower_io_to_mem(struct radv_device *device, struct radv_shader_stage *s nir_tcs_info tcs_info; nir_gather_tcs_info(nir, &tcs_info, nir->info.tess._primitive_mode, nir->info.tess.spacing); ac_nir_tess_io_info tess_io_info; - ac_nir_get_tess_io_info(nir, &tcs_info, info->tcs.tes_inputs_read, info->tcs.tes_patch_inputs_read, - &tess_io_info); + ac_nir_get_tess_io_info(nir, &tcs_info, info->tcs.tes_inputs_read, info->tcs.tes_patch_inputs_read, map_output, + true, &tess_io_info); NIR_PASS(_, nir, ac_nir_lower_hs_outputs_to_mem, &tcs_info, &tess_io_info, map_output, pdev->info.gfx_level, info->wave_size); diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index d0400d31037..fa12471030f 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -3618,8 +3618,7 @@ radv_emit_patch_control_points(struct radv_cmd_buffer *cmd_buffer) if (cmd_buffer->state.uses_dynamic_patch_control_points) { radv_get_tess_wg_info(pdev, &tcs->info.tcs.io_info, tcs->info.tcs.tcs_vertices_out, d->vk.ts.patch_control_points, /* TODO: This should be only inputs in LDS (not VGPR inputs) to reduce LDS usage */ - vs->info.vs.num_linked_outputs, tcs->info.tcs.num_linked_outputs, - tcs->info.tcs.num_linked_patch_outputs, &cmd_buffer->state.tess_num_patches, + vs->info.vs.num_linked_outputs, &cmd_buffer->state.tess_num_patches, &cmd_buffer->state.tess_lds_size); } @@ -10646,12 +10645,13 @@ radv_emit_tess_state(struct radv_cmd_buffer *cmd_buffer) unsigned tcs_out_mem_attrib_stride = align(cmd_buffer->state.tess_num_patches * tcs->info.tcs.tcs_vertices_out * 16, 256) / 256; - uint32_t tmp = SET_SGPR_FIELD(TCS_OFFCHIP_LAYOUT_NUM_PATCHES, cmd_buffer->state.tess_num_patches) | - SET_SGPR_FIELD(TCS_OFFCHIP_LAYOUT_TCS_MEM_ATTRIB_STRIDE, tcs_out_mem_attrib_stride) | - SET_SGPR_FIELD(TCS_OFFCHIP_LAYOUT_NUM_LS_OUTPUTS, vs->info.vs.num_linked_outputs) | - SET_SGPR_FIELD(TCS_OFFCHIP_LAYOUT_NUM_HS_OUTPUTS, tcs->info.tcs.num_linked_outputs) | - SET_SGPR_FIELD(TCS_OFFCHIP_LAYOUT_TES_READS_TF, tes->info.tes.reads_tess_factors) | - SET_SGPR_FIELD(TCS_OFFCHIP_LAYOUT_PRIMITIVE_MODE, tes->info.tes._primitive_mode); + uint32_t tmp = + SET_SGPR_FIELD(TCS_OFFCHIP_LAYOUT_NUM_PATCHES, cmd_buffer->state.tess_num_patches) | + SET_SGPR_FIELD(TCS_OFFCHIP_LAYOUT_TCS_MEM_ATTRIB_STRIDE, tcs_out_mem_attrib_stride) | + SET_SGPR_FIELD(TCS_OFFCHIP_LAYOUT_NUM_LS_OUTPUTS, vs->info.vs.num_linked_outputs) | + SET_SGPR_FIELD(TCS_OFFCHIP_LAYOUT_NUM_HS_OUTPUTS, tcs->info.tcs.io_info.highest_remapped_vram_output) | + SET_SGPR_FIELD(TCS_OFFCHIP_LAYOUT_TES_READS_TF, tes->info.tes.reads_tess_factors) | + SET_SGPR_FIELD(TCS_OFFCHIP_LAYOUT_PRIMITIVE_MODE, tes->info.tes._primitive_mode); tcs_offchip_layout = tmp | SET_SGPR_FIELD(TCS_OFFCHIP_LAYOUT_PATCH_VERTICES_IN, d->vk.ts.patch_control_points - 1); tes_offchip_layout = diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index e042223f8b2..d6f2acb2904 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -977,7 +977,8 @@ radv_GetPipelineExecutableStatisticsKHR(VkDevice _device, const VkPipelineExecut } /* TCS -> TES outputs */ - s->value.u64 += shader->info.tcs.num_linked_outputs + shader->info.tcs.num_linked_patch_outputs; + s->value.u64 += shader->info.tcs.io_info.highest_remapped_vram_output + + shader->info.tcs.io_info.highest_remapped_vram_patch_output; break; case MESA_SHADER_TESS_EVAL: diff --git a/src/amd/vulkan/radv_pipeline_graphics.c b/src/amd/vulkan/radv_pipeline_graphics.c index 02b8a631c5f..049777e0737 100644 --- a/src/amd/vulkan/radv_pipeline_graphics.c +++ b/src/amd/vulkan/radv_pipeline_graphics.c @@ -1508,8 +1508,6 @@ radv_graphics_shaders_fill_linked_tcs_tes_io_info(struct radv_shader_stage *tcs_ const unsigned num_reserved_patch_slots = util_bitcount64(tess_lvl_mask) + util_bitcount64(tes_stage->nir->info.patch_inputs_read); - tcs_stage->info.tcs.num_linked_outputs = num_reserved_slots; - tcs_stage->info.tcs.num_linked_patch_outputs = num_reserved_patch_slots; tcs_stage->info.outputs_linked = true; tes_stage->info.tes.num_linked_inputs = num_reserved_slots; diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index 1327e360747..b606dc813b5 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -3604,14 +3604,12 @@ radv_get_user_sgpr(const struct radv_shader *shader, int idx) void radv_get_tess_wg_info(const struct radv_physical_device *pdev, const ac_nir_tess_io_info *io_info, unsigned tcs_vertices_out, unsigned tcs_num_input_vertices, unsigned tcs_num_lds_inputs, - unsigned tcs_num_vram_outputs, unsigned tcs_num_vram_patch_outputs, unsigned *num_patches_per_wg, - unsigned *hw_lds_size) + unsigned *num_patches_per_wg, unsigned *hw_lds_size) { const uint32_t lds_input_vertex_size = get_tcs_input_vertex_stride(tcs_num_lds_inputs); ac_nir_compute_tess_wg_info(&pdev->info, io_info, tcs_vertices_out, pdev->ge_wave_size, false, - tcs_num_input_vertices, lds_input_vertex_size, tcs_num_vram_outputs, - tcs_num_vram_patch_outputs, num_patches_per_wg, hw_lds_size); + tcs_num_input_vertices, lds_input_vertex_size, 0, num_patches_per_wg, hw_lds_size); } VkResult diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index 0ae3e8216f9..129b2ebd246 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -674,7 +674,6 @@ get_tcs_input_vertex_stride(unsigned tcs_num_inputs) void radv_get_tess_wg_info(const struct radv_physical_device *pdev, const ac_nir_tess_io_info *io_info, unsigned tcs_vertices_out, unsigned tcs_num_input_vertices, unsigned tcs_num_lds_inputs, - unsigned tcs_num_vram_outputs, unsigned tcs_num_vram_patch_outputs, unsigned *num_patches_per_wg, unsigned *hw_lds_size); void radv_lower_ngg(struct radv_device *device, struct radv_shader_stage *ngg_stage, diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c index 26d5e3aa2ac..fbf107a3873 100644 --- a/src/amd/vulkan/radv_shader_info.c +++ b/src/amd/vulkan/radv_shader_info.c @@ -631,10 +631,11 @@ gather_shader_info_tcs(struct radv_device *device, const nir_shader *nir, const struct radv_graphics_state_key *gfx_state, struct radv_shader_info *info) { const struct radv_physical_device *pdev = radv_device_physical(device); + ac_nir_map_io_driver_location map_output = info->outputs_linked ? NULL : radv_map_io_driver_location; nir_tcs_info tcs_info; nir_gather_tcs_info(nir, &tcs_info, nir->info.tess._primitive_mode, nir->info.tess.spacing); - ac_nir_get_tess_io_info(nir, &tcs_info, ~0ull, ~0, &info->tcs.io_info); + ac_nir_get_tess_io_info(nir, &tcs_info, ~0ull, ~0, map_output, true, &info->tcs.io_info); info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out; info->tcs.tes_inputs_read = ~0ULL; @@ -642,19 +643,12 @@ gather_shader_info_tcs(struct radv_device *device, const nir_shader *nir, if (!info->inputs_linked) info->tcs.num_linked_inputs = util_last_bit64(radv_gather_unlinked_io_mask(nir->info.inputs_read)); - if (!info->outputs_linked) { - info->tcs.num_linked_outputs = util_last_bit64(radv_gather_unlinked_io_mask( - nir->info.outputs_written & ~(VARYING_BIT_TESS_LEVEL_OUTER | VARYING_BIT_TESS_LEVEL_INNER))); - info->tcs.num_linked_patch_outputs = util_last_bit64( - radv_gather_unlinked_patch_io_mask(nir->info.outputs_written, nir->info.patch_outputs_written)); - } if (gfx_state->ts.patch_control_points) { radv_get_tess_wg_info(pdev, &info->tcs.io_info, nir->info.tess.tcs_vertices_out, gfx_state->ts.patch_control_points, /* TODO: This should be only inputs in LDS (not VGPR inputs) to reduce LDS usage */ - info->tcs.num_linked_inputs, info->tcs.num_linked_outputs, - info->tcs.num_linked_patch_outputs, &info->num_tess_patches, &info->tcs.num_lds_blocks); + info->tcs.num_linked_inputs, &info->num_tess_patches, &info->tcs.num_lds_blocks); } } diff --git a/src/amd/vulkan/radv_shader_info.h b/src/amd/vulkan/radv_shader_info.h index b8218b0b3fd..50679cf2f00 100644 --- a/src/amd/vulkan/radv_shader_info.h +++ b/src/amd/vulkan/radv_shader_info.h @@ -243,9 +243,7 @@ struct radv_shader_info { uint64_t tes_patch_inputs_read; unsigned tcs_vertices_out; uint32_t num_lds_blocks; - uint8_t num_linked_inputs; /* Number of reserved per-vertex input slots in LDS. */ - uint8_t num_linked_outputs; /* Number of reserved per-vertex output slots in VRAM. */ - uint8_t num_linked_patch_outputs; /* Number of reserved per-patch output slots in VRAM. */ + uint8_t num_linked_inputs; /* Number of reserved per-vertex input slots in LDS. */ bool tes_reads_tess_factors : 1; } tcs; struct { diff --git a/src/gallium/drivers/radeonsi/si_nir_lower_abi.c b/src/gallium/drivers/radeonsi/si_nir_lower_abi.c index 0258fe35c25..617a1ff96fd 100644 --- a/src/gallium/drivers/radeonsi/si_nir_lower_abi.c +++ b/src/gallium/drivers/radeonsi/si_nir_lower_abi.c @@ -309,7 +309,7 @@ static bool lower_intrinsic(nir_builder *b, nir_instr *instr, struct lower_abi_s nir_def *num_tcs_mem_outputs; if (stage == MESA_SHADER_TESS_CTRL) - num_tcs_mem_outputs = nir_imm_int(b, util_last_bit64(sel->info.tcs_outputs_written_for_tes)); + num_tcs_mem_outputs = nir_imm_int(b, sel->info.tess_io_info.highest_remapped_vram_output); else num_tcs_mem_outputs = ac_nir_unpack_arg(b, &args->ac, args->tcs_offchip_layout, 23, 6); diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index bdfba39f1c1..af85c392dba 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -716,7 +716,7 @@ void si_shader_dump_stats_for_shader_db(struct si_screen *screen, struct si_shad if (shader->key.ge.as_ls) num_ls_outputs = si_shader_lshs_vertex_stride(shader) / 16; else if (shader->selector->stage == MESA_SHADER_TESS_CTRL) - num_hs_outputs = util_last_bit64(shader->selector->info.tcs_outputs_written_for_tes); + num_hs_outputs = shader->selector->info.tess_io_info.highest_remapped_vram_output; else if (shader->key.ge.as_es) num_es_outputs = shader->selector->info.esgs_vertex_stride / 16; else if (shader->gs_copy_shader) @@ -745,7 +745,7 @@ void si_shader_dump_stats_for_shader_db(struct si_screen *screen, struct si_shad conf->lds_size, conf->scratch_bytes_per_wave, shader->info.max_simd_waves, conf->spilled_sgprs, conf->spilled_vgprs, shader->info.private_mem_vgprs, num_ls_outputs, num_hs_outputs, - util_last_bit(shader->selector->info.patch_outputs_written_for_tes), + shader->selector->info.tess_io_info.highest_remapped_vram_patch_output, num_es_outputs, num_gs_outputs, num_vs_outputs, num_ps_outputs, shader->selector->info.base.num_inlinable_uniforms, shader->selector->info.has_divergent_loop, @@ -1041,7 +1041,7 @@ static void si_dump_shader_key(const struct si_shader *shader, FILE *f) } } -static unsigned si_map_io_driver_location(unsigned semantic) +unsigned si_map_io_driver_location(unsigned semantic) { if ((semantic >= VARYING_SLOT_PATCH0 && semantic < VARYING_SLOT_TESS_MAX) || semantic == VARYING_SLOT_TESS_LEVEL_INNER || @@ -1088,7 +1088,8 @@ static bool si_lower_io_to_mem(struct si_shader *shader, nir_shader *nir) nir_gather_tcs_info(nir, &tcs_info, nir->info.tess._primitive_mode, nir->info.tess.spacing); ac_nir_tess_io_info tess_io_info; - ac_nir_get_tess_io_info(nir, &tcs_info, ~0ull, ~0, &tess_io_info); + ac_nir_get_tess_io_info(nir, &tcs_info, ~0ull, ~0, si_map_io_driver_location, false, + &tess_io_info); NIR_PASS_V(nir, ac_nir_lower_hs_outputs_to_mem, &tcs_info, &tess_io_info, si_map_io_driver_location, sel->screen->info.gfx_level, shader->wave_size); diff --git a/src/gallium/drivers/radeonsi/si_shader.h b/src/gallium/drivers/radeonsi/si_shader.h index 8037d066304..36c4df7df1e 100644 --- a/src/gallium/drivers/radeonsi/si_shader.h +++ b/src/gallium/drivers/radeonsi/si_shader.h @@ -891,6 +891,7 @@ struct si_shader_part { /* si_shader.c */ struct ac_rtld_binary; +unsigned si_map_io_driver_location(unsigned semantic); bool si_compile_shader(struct si_screen *sscreen, struct ac_llvm_compiler *compiler, struct si_shader *shader, struct util_debug_callback *debug); bool si_create_shader_variant(struct si_screen *sscreen, struct ac_llvm_compiler *compiler, diff --git a/src/gallium/drivers/radeonsi/si_shader_info.c b/src/gallium/drivers/radeonsi/si_shader_info.c index 10935c2c5a6..9d5875c9d7e 100644 --- a/src/gallium/drivers/radeonsi/si_shader_info.c +++ b/src/gallium/drivers/radeonsi/si_shader_info.c @@ -197,12 +197,6 @@ static void scan_io_usage(const nir_shader *nir, struct si_shader_info *info, info->tess_levels_written_for_tes |= BITFIELD_BIT(ac_shader_io_get_unique_index_patch(slot_semantic)); } - } else if (slot_semantic >= VARYING_SLOT_PATCH0 && - slot_semantic < VARYING_SLOT_TESS_MAX) { - if (!nir_intrinsic_io_semantics(intr).no_varying) { - info->patch_outputs_written_for_tes |= - BITFIELD_BIT(ac_shader_io_get_unique_index_patch(slot_semantic)); - } } else if ((slot_semantic <= VARYING_SLOT_VAR31 || slot_semantic >= VARYING_SLOT_VAR0_16BIT) && slot_semantic != VARYING_SLOT_EDGE) { @@ -217,12 +211,8 @@ static void scan_io_usage(const nir_shader *nir, struct si_shader_info *info, /* LAYER and VIEWPORT have no effect if they don't feed the rasterizer. */ if (slot_semantic != VARYING_SLOT_LAYER && - slot_semantic != VARYING_SLOT_VIEWPORT) { + slot_semantic != VARYING_SLOT_VIEWPORT) info->ls_es_outputs_written |= bit; - - if (!nir_intrinsic_io_semantics(intr).no_varying) - info->tcs_outputs_written_for_tes |= bit; - } } } @@ -499,7 +489,8 @@ void si_nir_scan_shader(struct si_screen *sscreen, struct nir_shader *nir, nir_tcs_info tcs_info; nir_gather_tcs_info(nir, &tcs_info, nir->info.tess._primitive_mode, nir->info.tess.spacing); - ac_nir_get_tess_io_info(nir, &tcs_info, ~0ull, ~0, &info->tess_io_info); + ac_nir_get_tess_io_info(nir, &tcs_info, ~0ull, ~0, si_map_io_driver_location, false, + &info->tess_io_info); } /* tess factors are loaded as input instead of system value */ diff --git a/src/gallium/drivers/radeonsi/si_shader_info.h b/src/gallium/drivers/radeonsi/si_shader_info.h index 49058d26b9a..eb831bda96d 100644 --- a/src/gallium/drivers/radeonsi/si_shader_info.h +++ b/src/gallium/drivers/radeonsi/si_shader_info.h @@ -108,8 +108,6 @@ struct si_shader_info { /* For VS before {TCS, TES, GS} and TES before GS. */ uint64_t ls_es_outputs_written; /* "get_unique_index" bits */ uint64_t outputs_written_before_ps; /* "get_unique_index" bits */ - uint64_t tcs_outputs_written_for_tes; /* "get_unique_index" bits */ - uint32_t patch_outputs_written_for_tes; /* "get_unique_index_patch" bits */ uint32_t tess_levels_written_for_tes; /* "get_unique_index_patch" bits */ uint8_t clipdist_mask; diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.cpp b/src/gallium/drivers/radeonsi/si_state_shaders.cpp index 2eb1b2075c0..51c6b3bd58f 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.cpp +++ b/src/gallium/drivers/radeonsi/si_state_shaders.cpp @@ -4809,19 +4809,16 @@ void si_update_tess_io_layout_state(struct si_context *sctx) */ unsigned num_tcs_output_cp = tcs->info.base.tess.tcs_vertices_out; unsigned lds_input_vertex_size = si_shader_lshs_vertex_stride(ls_current); - unsigned num_mem_tcs_outputs = util_last_bit64(tcs->info.tcs_outputs_written_for_tes); - unsigned num_mem_tcs_patch_outputs = - util_last_bit(tcs->info.patch_outputs_written_for_tes | - (!ls_current->is_monolithic || ls_current->key.ge.opt.tes_reads_tess_factors ? - tcs->info.tess_levels_written_for_tes : 0)); + unsigned num_remapped_tess_level_outputs = + util_last_bit(!ls_current->is_monolithic || ls_current->key.ge.opt.tes_reads_tess_factors ? + tcs->info.tess_levels_written_for_tes : 0); unsigned num_patches, lds_size; /* Compute NUM_PATCHES and LDS_SIZE. */ ac_nir_compute_tess_wg_info(&sctx->screen->info, &tcs->info.tess_io_info, tcs->info.base.tess.tcs_vertices_out, ls_current->wave_size, tess_uses_primid, num_tcs_input_cp, lds_input_vertex_size, - num_mem_tcs_outputs, num_mem_tcs_patch_outputs, - &num_patches, &lds_size); + num_remapped_tess_level_outputs, &num_patches, &lds_size); if (sctx->num_patches_per_workgroup != num_patches) { sctx->num_patches_per_workgroup = num_patches; @@ -4838,7 +4835,7 @@ void si_update_tess_io_layout_state(struct si_context *sctx) assert(num_patches <= 127); assert(tcs_mem_attrib_stride <= 31); assert(num_lds_vs_outputs <= 63); - assert(num_mem_tcs_outputs <= 63); + assert(tcs->info.tess_io_info.highest_remapped_vram_output <= 63); uint64_t ring_va = sctx->ws->cs_is_secure(&sctx->gfx_cs) ? @@ -4847,7 +4844,8 @@ void si_update_tess_io_layout_state(struct si_context *sctx) assert((ring_va & BITFIELD_MASK(19)) == 0); unsigned shared_fields = num_patches | (tcs_mem_attrib_stride << 12) | - (num_lds_vs_outputs << 17) | (num_mem_tcs_outputs << 23); + (num_lds_vs_outputs << 17) | + (tcs->info.tess_io_info.highest_remapped_vram_output << 23); sctx->tes_offchip_ring_va_sgpr = ring_va; sctx->tcs_offchip_layout = (sctx->tcs_offchip_layout & 0xe0000000) |