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brw/nir: add intrinsics to read attribute payload register indirectly

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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34109>
This commit is contained in:
Lionel Landwerlin
2025-04-29 12:50:42 +03:00
committed by Marge Bot
parent ef17fbf8e5
commit 9d342081e7
7 changed files with 51 additions and 3 deletions
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src/intel/compiler/brw_lower_simd_width.cpp
+2 -1
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@@ -423,7 +423,8 @@ brw_get_lowered_simd_width(const brw_shader *shader, const brw_inst *inst)
swiz == BRW_SWIZZLE_XYXY || swiz == BRW_SWIZZLE_ZWZW ? 4 :
get_fpu_lowered_simd_width(shader, inst));
}
case SHADER_OPCODE_MOV_INDIRECT: {
case SHADER_OPCODE_MOV_INDIRECT:
case FS_OPCODE_READ_ATTRIBUTE_PAYLOAD: {
/* From IVB and HSW PRMs:
*
* "2.When the destination requires two registers and the sources are