diff --git a/src/gallium/drivers/asahi/agx_nir_lower_sysvals.c b/src/gallium/drivers/asahi/agx_nir_lower_sysvals.c index ffc35b16926..0d9b1f04346 100644 --- a/src/gallium/drivers/asahi/agx_nir_lower_sysvals.c +++ b/src/gallium/drivers/asahi/agx_nir_lower_sysvals.c @@ -111,20 +111,20 @@ lower_intrinsic(nir_builder *b, nir_intrinsic_instr *intr) case nir_intrinsic_load_ubo: return load_ubo(b, intr, s->ubo_base); case nir_intrinsic_load_vbo_base_agx: - return load_sysval_indirect(b, 1, 64, AGX_SYSVAL_TABLE_ROOT, - &u->vs.vbo_base, intr->src[0].ssa); + return load_sysval_indirect(b, 1, 64, AGX_SYSVAL_TABLE_ROOT, &u->vbo_base, + intr->src[0].ssa); case nir_intrinsic_load_blend_const_color_r_float: - return load_sysval_root(b, 1, 32, &u->fs.blend_constant[0]); + return load_sysval_root(b, 1, 32, &u->blend_constant[0]); case nir_intrinsic_load_blend_const_color_g_float: - return load_sysval_root(b, 1, 32, &u->fs.blend_constant[1]); + return load_sysval_root(b, 1, 32, &u->blend_constant[1]); case nir_intrinsic_load_blend_const_color_b_float: - return load_sysval_root(b, 1, 32, &u->fs.blend_constant[2]); + return load_sysval_root(b, 1, 32, &u->blend_constant[2]); case nir_intrinsic_load_blend_const_color_a_float: - return load_sysval_root(b, 1, 32, &u->fs.blend_constant[3]); + return load_sysval_root(b, 1, 32, &u->blend_constant[3]); case nir_intrinsic_load_api_sample_mask_agx: - return load_sysval_root(b, 1, 16, &u->fs.sample_mask); + return load_sysval_root(b, 1, 16, &u->sample_mask); case nir_intrinsic_load_sample_positions_agx: - return load_sysval_root(b, 1, 32, &u->fs.ppp_multisamplectl); + return load_sysval_root(b, 1, 32, &u->ppp_multisamplectl); case nir_intrinsic_load_ssbo_address: return load_sysval_indirect(b, 1, 64, stage_table(b), &s->ssbo_base, intr->src[0].ssa); @@ -134,17 +134,15 @@ lower_intrinsic(nir_builder *b, nir_intrinsic_instr *intr) case nir_intrinsic_load_num_workgroups: return load_sysval(b, 3, 32, AGX_SYSVAL_TABLE_GRID, 0); case nir_intrinsic_load_xfb_address: - return load_sysval_root(b, 1, 64, - &u->vs.xfb.base[nir_intrinsic_base(intr)]); + return load_sysval_root(b, 1, 64, &u->xfb.base[nir_intrinsic_base(intr)]); case nir_intrinsic_load_xfb_size: - return load_sysval_root(b, 1, 32, - &u->vs.xfb.size[nir_intrinsic_base(intr)]); + return load_sysval_root(b, 1, 32, &u->xfb.size[nir_intrinsic_base(intr)]); case nir_intrinsic_load_xfb_index_buffer: - return load_sysval_root(b, 1, 64, &u->vs.xfb.index_buffer); + return load_sysval_root(b, 1, 64, &u->xfb.index_buffer); case nir_intrinsic_load_base_vertex: - return load_sysval_root(b, 1, 32, &u->vs.xfb.base_vertex); + return load_sysval_root(b, 1, 32, &u->xfb.base_vertex); case nir_intrinsic_load_num_vertices: - return load_sysval_root(b, 1, 32, &u->vs.xfb.num_vertices); + return load_sysval_root(b, 1, 32, &u->xfb.num_vertices); default: return NULL; } diff --git a/src/gallium/drivers/asahi/agx_state.c b/src/gallium/drivers/asahi/agx_state.c index 7a59e29dfc8..2ab1f5c21cc 100644 --- a/src/gallium/drivers/asahi/agx_state.c +++ b/src/gallium/drivers/asahi/agx_state.c @@ -2259,8 +2259,6 @@ agx_build_pipeline(struct agx_batch *batch, struct agx_compiled_shader *cs, } } - batch->tables[AGX_SYSVAL_TABLE_ROOT] = agx_upload_uniforms(batch, stage); - for (unsigned i = 0; i < cs->push_range_count; ++i) { agx_usc_uniform(&b, cs->push[i].uniform, cs->push[i].length, batch->tables[cs->push[i].table] + cs->push[i].offset); @@ -2609,10 +2607,13 @@ agx_encode_state(struct agx_batch *batch, uint8_t *out, bool is_lines, struct agx_rasterizer *rast = ctx->rast; unsigned ppp_updates = 0; +#define IS_DIRTY(ST) !!(ctx->dirty & AGX_DIRTY_##ST) + agx_update_descriptors(batch, ctx->vs, PIPE_SHADER_VERTEX); agx_update_descriptors(batch, ctx->fs, PIPE_SHADER_FRAGMENT); -#define IS_DIRTY(ST) !!(ctx->dirty & AGX_DIRTY_##ST) + if (IS_DIRTY(VS) || IS_DIRTY(FS)) + agx_upload_uniforms(batch); if (IS_DIRTY(VS)) { agx_pack(out, VDM_STATE, cfg) { @@ -3274,6 +3275,7 @@ agx_launch_grid(struct pipe_context *pipe, const struct pipe_grid_info *info) agx_batch_add_bo(batch, cs->bo); agx_update_descriptors(batch, cs, PIPE_SHADER_COMPUTE); + agx_upload_uniforms(batch); /* TODO: Ensure space if we allow multiple kernels in a batch */ uint8_t *out = batch->encoder_current; diff --git a/src/gallium/drivers/asahi/agx_state.h b/src/gallium/drivers/asahi/agx_state.h index 9e16ee8ed6f..91fde22abec 100644 --- a/src/gallium/drivers/asahi/agx_state.h +++ b/src/gallium/drivers/asahi/agx_state.h @@ -122,26 +122,20 @@ struct PACKED agx_draw_uniforms { /* Pointers to the system value tables themselves (for indirection) */ uint64_t tables[AGX_NUM_SYSVAL_TABLES]; - union { - struct { - /* Vertex buffer object bases, if present */ - uint64_t vbo_base[PIPE_MAX_ATTRIBS]; + /* Vertex buffer object bases, if present */ + uint64_t vbo_base[PIPE_MAX_ATTRIBS]; - /* Transform feedback info for a transform feedback shader */ - struct agx_xfb_params xfb; - } vs; + /* Transform feedback info for a transform feedback shader */ + struct agx_xfb_params xfb; - struct { - /* Blend constant if any */ - float blend_constant[4]; + /* Blend constant if any */ + float blend_constant[4]; - /* Value of the ppp_multisamplectl control register */ - uint32_t ppp_multisamplectl; + /* Value of the ppp_multisamplectl control register */ + uint32_t ppp_multisamplectl; - /* glSampleMask */ - uint16_t sample_mask; - } fs; - }; + /* glSampleMask */ + uint16_t sample_mask; }; struct PACKED agx_stage_uniforms { @@ -706,8 +700,7 @@ agx_transfer(struct pipe_transfer *p) return (struct agx_transfer *)p; } -uint64_t agx_upload_uniforms(struct agx_batch *batch, - enum pipe_shader_type stage); +void agx_upload_uniforms(struct agx_batch *batch); uint64_t agx_upload_stage_uniforms(struct agx_batch *batch, uint64_t textures, enum pipe_shader_type stage); diff --git a/src/gallium/drivers/asahi/agx_uniforms.c b/src/gallium/drivers/asahi/agx_uniforms.c index bd9465b0047..07b160b6a17 100644 --- a/src/gallium/drivers/asahi/agx_uniforms.c +++ b/src/gallium/drivers/asahi/agx_uniforms.c @@ -50,49 +50,40 @@ agx_vertex_buffer_ptr(struct agx_batch *batch, unsigned vbo) } } -uint64_t -agx_upload_uniforms(struct agx_batch *batch, enum pipe_shader_type stage) +void +agx_upload_uniforms(struct agx_batch *batch) { struct agx_context *ctx = batch->ctx; struct agx_ptr root_ptr = agx_pool_alloc_aligned( &batch->pool, sizeof(struct agx_draw_uniforms), 16); + batch->tables[AGX_SYSVAL_TABLE_ROOT] = root_ptr.gpu; + struct agx_draw_uniforms uniforms = { - .tables = - { - [AGX_SYSVAL_TABLE_ROOT] = root_ptr.gpu, - }, + .sample_mask = ctx->sample_mask, + .ppp_multisamplectl = batch->ppp_multisamplectl, }; - STATIC_ASSERT(AGX_SYSVAL_TABLE_ROOT == 0); - memcpy(&uniforms.tables[1], &batch->tables[1], - sizeof(batch->tables[0]) * (ARRAY_SIZE(batch->tables) - 1)); + memcpy(&uniforms.tables, &batch->tables, sizeof(batch->tables)); - if (stage == PIPE_SHADER_VERTEX) { - u_foreach_bit(vbo, ctx->vb_mask) { - uniforms.vs.vbo_base[vbo] = agx_vertex_buffer_ptr(batch, vbo); - } - - if (ctx->streamout.key.active) { - uniforms.vs.xfb = ctx->streamout.params; - - for (unsigned i = 0; i < batch->ctx->streamout.num_targets; ++i) { - uint32_t size = 0; - uniforms.vs.xfb.base[i] = agx_batch_get_so_address(batch, i, &size); - uniforms.vs.xfb.size[i] = size; - } - } - } else if (stage == PIPE_SHADER_FRAGMENT) { - memcpy(uniforms.fs.blend_constant, &ctx->blend_color, - sizeof(ctx->blend_color)); - - uniforms.fs.sample_mask = ctx->sample_mask; - uniforms.fs.ppp_multisamplectl = batch->ppp_multisamplectl; + u_foreach_bit(vbo, ctx->vb_mask) { + uniforms.vbo_base[vbo] = agx_vertex_buffer_ptr(batch, vbo); } + if (ctx->streamout.key.active) { + uniforms.xfb = ctx->streamout.params; + + for (unsigned i = 0; i < batch->ctx->streamout.num_targets; ++i) { + uint32_t size = 0; + uniforms.xfb.base[i] = agx_batch_get_so_address(batch, i, &size); + uniforms.xfb.size[i] = size; + } + } + + memcpy(uniforms.blend_constant, &ctx->blend_color, sizeof(ctx->blend_color)); + memcpy(root_ptr.cpu, &uniforms, sizeof(uniforms)); - return root_ptr.gpu; } uint64_t