diff --git a/src/asahi/layout/layout.c b/src/asahi/layout/layout.c
index 7b57d6fb266..95e76d8e58e 100644
--- a/src/asahi/layout/layout.c
+++ b/src/asahi/layout/layout.c
@@ -291,7 +291,7 @@ ail_make_miptree(struct ail_layout *layout)
    }
 
    assert(!(layout->writeable_image &&
-            layout->tiling == AIL_TILING_TWIDDLED_COMPRESSED) &&
+            layout->tiling == AIL_TILING_GPU_COMPRESSED) &&
           "Writeable images must not be compressed");
 
    /* Hardware strides are based on the maximum number of levels, so always
@@ -313,10 +313,10 @@ ail_make_miptree(struct ail_layout *layout)
    case AIL_TILING_LINEAR:
       ail_initialize_linear(layout);
       break;
-   case AIL_TILING_TWIDDLED:
+   case AIL_TILING_GPU:
       ail_initialize_twiddled(layout);
       break;
-   case AIL_TILING_TWIDDLED_COMPRESSED:
+   case AIL_TILING_GPU_COMPRESSED:
       ail_initialize_twiddled(layout);
       ail_initialize_compression(layout);
       break;
diff --git a/src/asahi/layout/layout.h b/src/asahi/layout/layout.h
index 23cfaf7608b..71a81c639a6 100644
--- a/src/asahi/layout/layout.h
+++ b/src/asahi/layout/layout.h
@@ -27,14 +27,14 @@ enum ail_tiling {
    AIL_TILING_LINEAR,
 
    /**
-    * Twiddled (Morton order). Always allowed.
+    * GPU-tiled. Always allowed.
     */
-   AIL_TILING_TWIDDLED,
+   AIL_TILING_GPU,
 
    /**
-    * Twiddled (Morton order) with compression.
+    * GPU-tiled with compression.
     */
-   AIL_TILING_TWIDDLED_COMPRESSED,
+   AIL_TILING_GPU_COMPRESSED,
 };
 
 /*
@@ -104,14 +104,14 @@ struct ail_layout {
    uint64_t level_offsets_compressed_B[AIL_MAX_MIP_LEVELS];
 
    /**
-    * If tiling is TWIDDLED, the tile size used for each mip level within a
+    * If tiling is nonlinear, the tile size used for each mip level within a
     * layer. Calculating tile sizes is the sole responsibility of
     * ail_initialized_twiddled.
     */
    struct ail_tile tilesize_el[AIL_MAX_MIP_LEVELS];
 
    /**
-    * If tiling is TWIDDLED, the stride in elements used for each mip level
+    * If tiling is nonlinear, the stride in elements used for each mip level
     * within a layer. Calculating level strides is the sole responsibility of
     * ail_initialized_twiddled. This is necessary because compressed pixel
     * formats may add extra stride padding.
@@ -180,7 +180,7 @@ ail_get_linear_stride_B(const struct ail_layout *layout, ASSERTED uint8_t level)
 /*
  * For WSI purposes, we need to associate a stride with all layouts. In the
  * hardware, only strided linear images have an associated stride, there is no
- * natural stride associated with twiddled images. However, various clients
+ * natural stride associated with nonlinear images. However, various clients
  * assert that the stride is valid for the image if it were linear (even if it
  * is in fact not linear). In those cases, by convention we use the minimum
  * valid such stride.
@@ -267,8 +267,8 @@ static inline uint32_t
 ail_get_twiddled_block_B(const struct ail_layout *layout, unsigned level,
                          uint32_t x_px, uint32_t y_px, uint32_t z_px)
 {
-   assert(layout->tiling == AIL_TILING_TWIDDLED ||
-          layout->tiling == AIL_TILING_TWIDDLED_COMPRESSED);
+   assert(layout->tiling == AIL_TILING_GPU ||
+          layout->tiling == AIL_TILING_GPU_COMPRESSED);
 
    assert(level < layout->levels);
 
@@ -324,7 +324,7 @@ ail_metadata_height_tl(struct ail_layout *layout, unsigned level)
 static inline bool
 ail_is_compressed(const struct ail_layout *layout)
 {
-   return layout->tiling == AIL_TILING_TWIDDLED_COMPRESSED;
+   return layout->tiling == AIL_TILING_GPU_COMPRESSED;
 }
 
 /*
@@ -350,9 +350,9 @@ ail_is_level_twiddled_uncompressed(const struct ail_layout *layout,
                                    unsigned level)
 {
    switch (layout->tiling) {
-   case AIL_TILING_TWIDDLED:
+   case AIL_TILING_GPU:
       return true;
-   case AIL_TILING_TWIDDLED_COMPRESSED:
+   case AIL_TILING_GPU_COMPRESSED:
       return !ail_is_level_compressed(layout, level);
    default:
       return false;
@@ -533,9 +533,9 @@ ail_drm_modifier_to_tiling(uint64_t modifier)
    case DRM_FORMAT_MOD_LINEAR:
       return AIL_TILING_LINEAR;
    case DRM_FORMAT_MOD_APPLE_TWIDDLED:
-      return AIL_TILING_TWIDDLED;
+      return AIL_TILING_GPU;
    case DRM_FORMAT_MOD_APPLE_TWIDDLED_COMPRESSED:
-      return AIL_TILING_TWIDDLED_COMPRESSED;
+      return AIL_TILING_GPU_COMPRESSED;
    default:
       unreachable("Unsupported modifier");
    }
diff --git a/src/asahi/layout/tests/test-generated.cpp b/src/asahi/layout/tests/test-generated.cpp
index e4654c5edf6..4d2982b7e99 100644
--- a/src/asahi/layout/tests/test-generated.cpp
+++ b/src/asahi/layout/tests/test-generated.cpp
@@ -66,7 +66,7 @@ TEST(Generated, CompTwiddled)
          .depth_px = test.depth,
          .sample_count_sa = 1,
          .levels = test.levels,
-         .tiling = AIL_TILING_TWIDDLED_COMPRESSED,
+         .tiling = AIL_TILING_GPU_COMPRESSED,
          .format = test.format,
       };
 
@@ -91,7 +91,7 @@ TEST(Generated, UncompTwiddled)
          .depth_px = test.depth,
          .sample_count_sa = 1,
          .levels = test.levels,
-         .tiling = AIL_TILING_TWIDDLED,
+         .tiling = AIL_TILING_GPU,
          .format = test.format,
       };
 
@@ -116,7 +116,7 @@ TEST(Generated, Miptree2D)
          .depth_px = 1,
          .sample_count_sa = 1,
          .levels = test.levels,
-         .tiling = AIL_TILING_TWIDDLED,
+         .tiling = AIL_TILING_GPU,
          .format = test.format,
       };
 
@@ -143,8 +143,8 @@ TEST(Generated, MSAA)
          .depth_px = test.depth,
          .sample_count_sa = test.samples,
          .levels = test.levels,
-         .tiling = test.is_compressed ? AIL_TILING_TWIDDLED_COMPRESSED
-                                      : AIL_TILING_TWIDDLED,
+         .tiling =
+            test.is_compressed ? AIL_TILING_GPU_COMPRESSED : AIL_TILING_GPU,
          .format = test.format,
       };
 
diff --git a/src/asahi/layout/tests/test-layout.cpp b/src/asahi/layout/tests/test-layout.cpp
index 9d8ae5170d4..4f46144c144 100644
--- a/src/asahi/layout/tests/test-layout.cpp
+++ b/src/asahi/layout/tests/test-layout.cpp
@@ -14,7 +14,7 @@ TEST(Cubemap, Nonmipmapped)
       .depth_px = 6,
       .sample_count_sa = 1,
       .levels = 1,
-      .tiling = AIL_TILING_TWIDDLED,
+      .tiling = AIL_TILING_GPU,
       .format = PIPE_FORMAT_R8G8B8A8_UNORM,
    };
 
@@ -32,7 +32,7 @@ TEST(Cubemap, RoundsToOnePage)
       .depth_px = 6,
       .sample_count_sa = 1,
       .levels = 6,
-      .tiling = AIL_TILING_TWIDDLED,
+      .tiling = AIL_TILING_GPU,
       .format = PIPE_FORMAT_R32_FLOAT,
    };
 
@@ -73,7 +73,7 @@ TEST(Miptree, AllMipLevels)
       .depth_px = 1,
       .sample_count_sa = 1,
       .levels = 11,
-      .tiling = AIL_TILING_TWIDDLED,
+      .tiling = AIL_TILING_GPU,
       .format = PIPE_FORMAT_R8G8B8A8_UINT,
    };
 
@@ -92,7 +92,7 @@ TEST(Miptree, SomeMipLevels)
       .depth_px = 1,
       .sample_count_sa = 1,
       .levels = 4,
-      .tiling = AIL_TILING_TWIDDLED,
+      .tiling = AIL_TILING_GPU,
       .format = PIPE_FORMAT_R8G8B8A8_UINT,
    };
 
@@ -111,7 +111,7 @@ TEST(Miptree, SmallPartialMiptree2DArray)
       .depth_px = 64,
       .sample_count_sa = 1,
       .levels = 4,
-      .tiling = AIL_TILING_TWIDDLED,
+      .tiling = AIL_TILING_GPU,
       .format = PIPE_FORMAT_R32_FLOAT,
    };
 
@@ -132,7 +132,7 @@ TEST(Miptree, SmallPartialMiptree3D)
       .sample_count_sa = 1,
       .levels = 4,
       .mipmapped_z = true,
-      .tiling = AIL_TILING_TWIDDLED,
+      .tiling = AIL_TILING_GPU,
       .format = PIPE_FORMAT_R32_FLOAT,
    };
 
diff --git a/src/asahi/layout/tests/test-twiddling.cpp b/src/asahi/layout/tests/test-twiddling.cpp
index 0e85fac3464..f0288318abd 100644
--- a/src/asahi/layout/tests/test-twiddling.cpp
+++ b/src/asahi/layout/tests/test-twiddling.cpp
@@ -134,7 +134,7 @@ test(unsigned width, unsigned height, unsigned rx, unsigned ry, unsigned rw,
       .depth_px = 1,
       .sample_count_sa = 1,
       .levels = 1,
-      .tiling = AIL_TILING_TWIDDLED,
+      .tiling = AIL_TILING_GPU,
       .format = format,
    };
 
diff --git a/src/asahi/lib/agx_helpers.h b/src/asahi/lib/agx_helpers.h
index d7833b3b46f..5dc52adb3b4 100644
--- a/src/asahi/lib/agx_helpers.h
+++ b/src/asahi/lib/agx_helpers.h
@@ -82,8 +82,8 @@ static inline enum agx_layout
 agx_translate_layout(enum ail_tiling tiling)
 {
    switch (tiling) {
-   case AIL_TILING_TWIDDLED:
-   case AIL_TILING_TWIDDLED_COMPRESSED:
+   case AIL_TILING_GPU:
+   case AIL_TILING_GPU_COMPRESSED:
       return AGX_LAYOUT_TWIDDLED;
    case AIL_TILING_LINEAR:
       return AGX_LAYOUT_LINEAR;
diff --git a/src/asahi/vulkan/hk_image.c b/src/asahi/vulkan/hk_image.c
index 8956ed7a8df..a782c8a8f2b 100644
--- a/src/asahi/vulkan/hk_image.c
+++ b/src/asahi/vulkan/hk_image.c
@@ -743,9 +743,9 @@ hk_map_tiling(struct hk_device *dev, const VkImageCreateInfo *info,
 
    case VK_IMAGE_TILING_OPTIMAL:
       if (hk_can_compress_create_info(dev, plane, info)) {
-         return AIL_TILING_TWIDDLED_COMPRESSED;
+         return AIL_TILING_GPU_COMPRESSED;
       } else {
-         return AIL_TILING_TWIDDLED;
+         return AIL_TILING_GPU;
       }
 
    case VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT:
@@ -907,7 +907,7 @@ hk_image_init(struct hk_device *dev, struct hk_image *image,
 
          .levels = pCreateInfo->mipLevels,
          .sample_count_sa = pCreateInfo->samples,
-         .writeable_image = tiling != AIL_TILING_TWIDDLED_COMPRESSED,
+         .writeable_image = tiling != AIL_TILING_GPU_COMPRESSED,
 
          /* TODO: Maybe optimize this, our GL driver doesn't bother though */
          .renderable = true,
diff --git a/src/asahi/vulkan/hk_image_view.c b/src/asahi/vulkan/hk_image_view.c
index bc026d2093e..0ef4065069d 100644
--- a/src/asahi/vulkan/hk_image_view.c
+++ b/src/asahi/vulkan/hk_image_view.c
@@ -351,9 +351,6 @@ pack_texture(struct hk_image_view *view, unsigned view_plane,
       if (layout->tiling == AIL_TILING_LINEAR) {
          cfg.stride = ail_get_linear_stride_B(layout, 0) - 16;
       } else {
-         assert(layout->tiling == AIL_TILING_TWIDDLED ||
-                layout->tiling == AIL_TILING_TWIDDLED_COMPRESSED);
-
          cfg.page_aligned_layers = layout->page_aligned_layers;
       }
    }
diff --git a/src/gallium/drivers/asahi/agx_pipe.c b/src/gallium/drivers/asahi/agx_pipe.c
index 1701259e4e2..348a8f85dab 100644
--- a/src/gallium/drivers/asahi/agx_pipe.c
+++ b/src/gallium/drivers/asahi/agx_pipe.c
@@ -90,8 +90,8 @@ void agx_init_state_functions(struct pipe_context *ctx);
 
 const static char *s_tiling[] = {
    [AIL_TILING_LINEAR] = "LINR",
-   [AIL_TILING_TWIDDLED] = "TWID",
-   [AIL_TILING_TWIDDLED_COMPRESSED] = "COMP",
+   [AIL_TILING_GPU] = "TWID",
+   [AIL_TILING_GPU_COMPRESSED] = "COMP",
 };
 
 #define rsrc_debug(res, ...)                                                   \
@@ -1167,7 +1167,7 @@ void
 agx_decompress(struct agx_context *ctx, struct agx_resource *rsrc,
                const char *reason)
 {
-   if (rsrc->layout.tiling == AIL_TILING_TWIDDLED_COMPRESSED) {
+   if (rsrc->layout.tiling == AIL_TILING_GPU_COMPRESSED) {
       perf_debug_ctx(ctx, "Decompressing resource due to %s", reason);
    } else if (!rsrc->layout.writeable_image) {
       perf_debug_ctx(ctx, "Reallocating image due to %s", reason);
diff --git a/src/gallium/drivers/asahi/agx_state.c b/src/gallium/drivers/asahi/agx_state.c
index d5d639d822b..d4ebdba7b3b 100644
--- a/src/gallium/drivers/asahi/agx_state.c
+++ b/src/gallium/drivers/asahi/agx_state.c
@@ -763,8 +763,8 @@ agx_pack_texture(void *out, struct agx_resource *rsrc,
       } else if (rsrc->layout.tiling == AIL_TILING_LINEAR) {
          cfg.stride = ail_get_linear_stride_B(&rsrc->layout, 0) - 16;
       } else {
-         assert(rsrc->layout.tiling == AIL_TILING_TWIDDLED ||
-                rsrc->layout.tiling == AIL_TILING_TWIDDLED_COMPRESSED);
+         assert(rsrc->layout.tiling == AIL_TILING_GPU ||
+                rsrc->layout.tiling == AIL_TILING_GPU_COMPRESSED);
 
          cfg.page_aligned_layers = rsrc->layout.page_aligned_layers;
       }
@@ -1321,7 +1321,7 @@ agx_batch_upload_pbe(struct agx_batch *batch, struct agx_pbe_packed *out,
 
          cfg.sample_count_log2_sw = util_logbase2(tex->base.nr_samples);
 
-         if (tex->layout.tiling == AIL_TILING_TWIDDLED || emrt) {
+         if (tex->layout.tiling == AIL_TILING_GPU || emrt) {
             struct ail_tile tile_size = tex->layout.tilesize_el[level];
             cfg.tile_width_sw = tile_size.width_el;
             cfg.tile_height_sw = tile_size.height_el;
@@ -4798,7 +4798,7 @@ agx_legalize_feedback_loops(struct agx_context *ctx)
             if (ctx->framebuffer.cbufs[cb] &&
                 agx_resource(ctx->framebuffer.cbufs[cb]->texture) == rsrc) {
 
-               if (rsrc->layout.tiling == AIL_TILING_TWIDDLED_COMPRESSED) {
+               if (rsrc->layout.tiling == AIL_TILING_GPU_COMPRESSED) {
                   /* Decompress if we can and shadow if we can't. */
                   if (rsrc->base.bind & PIPE_BIND_SHARED) {
                      struct agx_batch *batch = agx_get_batch(ctx);