From 99ae565af2b8724ce316d27d7e7382e34aab9a91 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= Date: Wed, 22 Nov 2023 07:36:36 -0800 Subject: [PATCH] anv: Prepare anv_device_get_pat_entry() for discrete GPUs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Roberto de Souza Reviewed-by: Lionel Landwerlin Part-of: --- src/intel/vulkan/anv_device.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index 1be4c158996..3795cadabea 100644 --- a/src/intel/vulkan/anv_device.c +++ b/src/intel/vulkan/anv_device.c @@ -5187,6 +5187,16 @@ const struct intel_device_info_pat_entry * anv_device_get_pat_entry(struct anv_device *device, enum anv_bo_alloc_flags alloc_flags) { + /* PAT indexes has no actual effect in DG2 and DG1, smem caches will always + * be snopped by GPU and lmem will always be WC. + * This might change in future discrete platforms. + */ + if (anv_physical_device_has_vram(device->physical)) { + if (alloc_flags & ANV_BO_ALLOC_NO_LOCAL_MEM) + return &device->info->pat.cached_coherent; + return &device->info->pat.writecombining; + } + if (alloc_flags & (ANV_BO_ALLOC_HOST_CACHED_COHERENT)) return &device->info->pat.cached_coherent; else if (alloc_flags & (ANV_BO_ALLOC_EXTERNAL | ANV_BO_ALLOC_SCANOUT))