diff --git a/src/freedreno/ir3/instr-a3xx.h b/src/freedreno/ir3/instr-a3xx.h
index 78178f9ade7..e9eaebc937c 100644
--- a/src/freedreno/ir3/instr-a3xx.h
+++ b/src/freedreno/ir3/instr-a3xx.h
@@ -373,6 +373,8 @@ typedef enum {
 
    OPC_ALIAS           = _OPC(7, 9),
 
+   OPC_CCINV           = _OPC(7, 10),
+
    /* meta instructions (category 8): */
 #define OPC_META 8
    /* placeholder instr to mark shader inputs: */
diff --git a/src/freedreno/ir3/ir3.h b/src/freedreno/ir3/ir3.h
index 13b137e4b3e..221080ba261 100644
--- a/src/freedreno/ir3/ir3.h
+++ b/src/freedreno/ir3/ir3.h
@@ -2536,6 +2536,7 @@ INSTR4(ATOMIC_S_XOR)
 /* cat7 instructions: */
 INSTR0(BAR)
 INSTR0(FENCE)
+INSTR0(CCINV)
 
 /* ************************************************************************* */
 #include "util/bitset.h"
diff --git a/src/freedreno/ir3/ir3_lexer.l b/src/freedreno/ir3/ir3_lexer.l
index da6a11b96a9..a76f68c3b8c 100644
--- a/src/freedreno/ir3/ir3_lexer.l
+++ b/src/freedreno/ir3/ir3_lexer.l
@@ -392,6 +392,7 @@ static int parse_reg(const char *str)
 "dccln.all"                       return TOKEN(T_OP_DCCLN);
 "dcinv.all"                       return TOKEN(T_OP_DCINV);
 "dcflu.all"                       return TOKEN(T_OP_DCFLU);
+"ccinv"                           return TOKEN(T_OP_CCINV);
 "lock"                            return TOKEN(T_OP_LOCK);
 "unlock"                          return TOKEN(T_OP_UNLOCK);
 "alias"                           return TOKEN(T_OP_ALIAS);
diff --git a/src/freedreno/ir3/ir3_parser.y b/src/freedreno/ir3/ir3_parser.y
index f975eadae4e..7d9742b6dcc 100644
--- a/src/freedreno/ir3/ir3_parser.y
+++ b/src/freedreno/ir3/ir3_parser.y
@@ -629,6 +629,7 @@ static void print_token(FILE *file, int type, YYSTYPE value)
 %token <tok> T_OP_DCCLN
 %token <tok> T_OP_DCINV
 %token <tok> T_OP_DCFLU
+%token <tok> T_OP_CCINV
 %token <tok> T_OP_LOCK
 %token <tok> T_OP_UNLOCK
 %token <tok> T_OP_ALIAS
@@ -1331,6 +1332,7 @@ cat7_alias_scope: T_MOD_TEX	{ instr->cat7.alias_scope = ALIAS_TEX; }
 cat7_instr:        cat7_barrier
 |                  cat7_data_cache
 |                  T_OP_SLEEP              { new_instr(OPC_SLEEP); }
+|                  T_OP_CCINV              { new_instr(OPC_CCINV); }
 |                  T_OP_ICINV              { new_instr(OPC_ICINV); }
 |                  T_OP_LOCK               { new_instr(OPC_LOCK); }
 |                  T_OP_UNLOCK             { new_instr(OPC_UNLOCK); }
diff --git a/src/freedreno/ir3/tests/disasm.c b/src/freedreno/ir3/tests/disasm.c
index d86991b8cf5..e809a879a0b 100644
--- a/src/freedreno/ir3/tests/disasm.c
+++ b/src/freedreno/ir3/tests/disasm.c
@@ -448,6 +448,8 @@ static const struct test {
    INSTR_6XX(f0420000_00000000, "(sy)bar.g"),
    INSTR_6XX(e1080000_00000000, "sleep.l"),
    INSTR_6XX(e2080000_00000000, "dccln.all"),
+   /* dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.payload_local.buffer.guard_local.buffer.comp */
+   INSTR_7XX(e2d20000_00000000, "ccinv"),
 
    INSTR_7XX(e3c20000_00000000, "lock"),
    INSTR_7XX(fbc21000_00000000, "(sy)(ss)(jp)lock"),
diff --git a/src/freedreno/isa/ir3-cat7.xml b/src/freedreno/isa/ir3-cat7.xml
index 45d90376128..0de4d3d2cfd 100644
--- a/src/freedreno/isa/ir3-cat7.xml
+++ b/src/freedreno/isa/ir3-cat7.xml
@@ -73,7 +73,7 @@ SOFTWARE.
 	</display>
 	<pattern low="45" high="50">xxxxxx</pattern>
 	<field   pos="51" 		   name="TYPE" type="#dccln-type"/>
-	<pattern low="52" high="54">xxx</pattern>
+	<pattern low="52" high="54">xx0</pattern>
 	<encode>
 		<!-- TODO: read handle type -->
 		<map name="TYPE">1</map>
@@ -145,6 +145,21 @@ SOFTWARE.
 	<pattern low="55" high="58">0110</pattern>
 </bitset>
 
+<bitset name="ccinv" extends="#instruction-cat7">
+	<doc>
+		_Presumably_ invalidates workgroup-wide cache for image/buffer data access.
+		So while "fence" is enough to synchronize data access inside a workgroup,
+		for cross-workgroup synchronization we have to invalidate that cache.
+	</doc>
+	<gen min="700"/>
+	<display>
+		{SY}{SS}{JP}{NAME}
+	</display>
+	<pattern low="45" high="50">x1xxxx</pattern>
+	<pattern low="51" high="54">1010</pattern>
+	<pattern low="55" high="58">0101</pattern>
+</bitset>
+
 <bitset name="lock" extends="#instruction-cat7">
 	<doc>
 		Are met at the end of compute shader: