diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h
index 046a1b6d359..c0864c64950 100644
--- a/src/intel/compiler/brw_compiler.h
+++ b/src/intel/compiler/brw_compiler.h
@@ -467,6 +467,8 @@ enum brw_param_builtin {
 #define BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(param) \
    (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) & 0x3)
 
+#define BRW_MAX_EMBEDDED_SAMPLERS (4096)
+
 enum brw_shader_reloc_id {
    BRW_SHADER_RELOC_CONST_DATA_ADDR_LOW,
    BRW_SHADER_RELOC_CONST_DATA_ADDR_HIGH,
@@ -474,6 +476,9 @@ enum brw_shader_reloc_id {
    BRW_SHADER_RELOC_RESUME_SBT_ADDR_LOW,
    BRW_SHADER_RELOC_RESUME_SBT_ADDR_HIGH,
    BRW_SHADER_RELOC_DESCRIPTORS_ADDR_HIGH,
+   BRW_SHADER_RELOC_EMBEDDED_SAMPLER_HANDLE,
+   BRW_SHADER_RELOC_LAST_EMBEDDED_SAMPLER_HANDLE =
+   BRW_SHADER_RELOC_EMBEDDED_SAMPLER_HANDLE + BRW_MAX_EMBEDDED_SAMPLERS - 1,
 };
 
 enum brw_shader_reloc_type {
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index f00b056aa7b..6d0aa389821 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -4643,13 +4643,25 @@ try_rebuild_resource(nir_to_brw_state &ntb, const brw::fs_builder &bld, nir_def
       } else {
          assert(def->parent_instr->type == nir_instr_type_intrinsic &&
                 (nir_instr_as_intrinsic(def->parent_instr)->intrinsic ==
-                 nir_intrinsic_load_uniform));
+                 nir_intrinsic_load_uniform ||
+                 nir_instr_as_intrinsic(def->parent_instr)->intrinsic ==
+                 nir_intrinsic_load_reloc_const_intel));
          nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(def->parent_instr);
-         unsigned base_offset = nir_intrinsic_base(intrin);
-         unsigned load_offset = nir_src_as_uint(intrin->src[0]);
-         fs_reg src(UNIFORM, base_offset / 4, BRW_REGISTER_TYPE_UD);
-         src.offset = load_offset + base_offset % 4;
-         return src;
+         switch (intrin->intrinsic) {
+         case nir_intrinsic_load_uniform: {
+            unsigned base_offset = nir_intrinsic_base(intrin);
+            unsigned load_offset = nir_src_as_uint(intrin->src[0]);
+            fs_reg src(UNIFORM, base_offset / 4, BRW_REGISTER_TYPE_UD);
+            src.offset = load_offset + base_offset % 4;
+            return src;
+         }
+
+         default:
+            /* Execute the code below, since we have to generate new
+             * instructions.
+             */
+            break;
+         }
       }
    }
 
@@ -4759,6 +4771,14 @@ try_rebuild_resource(nir_to_brw_state &ntb, const brw::fs_builder &bld, nir_def
             break;
          }
 
+         case nir_intrinsic_load_reloc_const_intel: {
+            uint32_t id = nir_intrinsic_param_idx(intrin);
+            fs_reg dst = ubld8.vgrf(BRW_REGISTER_TYPE_UD);
+            ntb.resource_insts[def->index] =
+               ubld8.emit(SHADER_OPCODE_MOV_RELOC_IMM, dst,
+                          brw_imm_ud(id), brw_imm_ud(0));
+         }
+
          default:
             break;
          }
@@ -8520,4 +8540,3 @@ nir_to_brw(fs_visitor *s)
 
    ralloc_free(ntb.mem_ctx);
 }
-