diff --git a/src/amd/common/ac_debug.c b/src/amd/common/ac_debug.c index dd049fe0816..9e6f4603f96 100644 --- a/src/amd/common/ac_debug.c +++ b/src/amd/common/ac_debug.c @@ -115,6 +115,10 @@ static const struct si_reg *find_register(enum chip_class chip_class, unsigned o unsigned table_size; switch (chip_class) { + case GFX11: + table = gfx11_reg_table; + table_size = ARRAY_SIZE(gfx11_reg_table); + break; case GFX10_3: case GFX10: table = gfx10_reg_table; diff --git a/src/amd/common/amd_family.h b/src/amd/common/amd_family.h index a5d854de567..fc3cb1e40d3 100644 --- a/src/amd/common/amd_family.h +++ b/src/amd/common/amd_family.h @@ -147,6 +147,7 @@ enum chip_class GFX9, GFX10, GFX10_3, + GFX11, NUM_GFX_VERSIONS, }; diff --git a/src/amd/common/meson.build b/src/amd/common/meson.build index 887bc300b32..1339748fce8 100644 --- a/src/amd/common/meson.build +++ b/src/amd/common/meson.build @@ -27,10 +27,12 @@ amd_json_files = [ '../registers/gfx9.json', '../registers/gfx10.json', '../registers/gfx103.json', + '../registers/gfx11.json', # Manually written: '../registers/pkt3.json', '../registers/gfx10-rsrc.json', + '../registers/gfx11-rsrc.json', '../registers/registers-manually-defined.json', ] diff --git a/src/amd/registers/makeregheader.py b/src/amd/registers/makeregheader.py index 37618840162..db5def95cac 100644 --- a/src/amd/registers/makeregheader.py +++ b/src/amd/registers/makeregheader.py @@ -48,6 +48,7 @@ CHIPS = [ Object(name='gfx9', disambiguation='GFX9'), Object(name='gfx10', disambiguation='GFX10'), Object(name='gfx103', disambiguation='GFX103'), + Object(name='gfx11', disambiguation='GFX11'), ] ######### END HARDCODED CONFIGURATION diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index d620b335049..f0f092d6649 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1160,9 +1160,9 @@ radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer) if (cmd_buffer->state.attachments) { struct radv_color_buffer_info *cb = &cmd_buffer->state.attachments[idx].cb; - format = G_028C70_FORMAT(cb->cb_color_info); + format = G_028C70_FORMAT_GFX6(cb->cb_color_info); swap = G_028C70_COMP_SWAP(cb->cb_color_info); - has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib); + has_alpha = !G_028C74_FORCE_DST_ALPHA_1_GFX6(cb->cb_color_attrib); } else { VkFormat fmt = cmd_buffer->state.pass->attachments[idx].format; format = radv_translate_colorformat(fmt); @@ -2504,7 +2504,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer) for (i = 0; i < subpass->color_count; ++i) { if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) { radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, - S_028C70_FORMAT(V_028C70_COLOR_INVALID)); + S_028C70_FORMAT_GFX6(V_028C70_COLOR_INVALID)); continue; } @@ -2532,7 +2532,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer) } for (; i < cmd_buffer->state.last_subpass_color_count; i++) { radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, - S_028C70_FORMAT(V_028C70_COLOR_INVALID)); + S_028C70_FORMAT_GFX6(V_028C70_COLOR_INVALID)); } cmd_buffer->state.last_subpass_color_count = subpass->color_count; diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index bd32d0bb225..6334f62b826 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -3678,7 +3678,7 @@ fill_geom_tess_rings(struct radv_queue *queue, uint32_t *map, bool add_sample_po /* stride 0, num records - size, add tid, swizzle, elsize4, index stride 64 */ desc[0] = esgs_va; - desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) | S_008F04_SWIZZLE_ENABLE(true); + desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) | S_008F04_SWIZZLE_ENABLE_GFX6(true); desc[2] = esgs_ring_size; desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) | S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) | @@ -3736,7 +3736,7 @@ fill_geom_tess_rings(struct radv_queue *queue, uint32_t *map, bool add_sample_po elsize 4, index stride 16 */ /* shader will patch stride and desc[2] */ desc[4] = gsvs_va; - desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32) | S_008F04_SWIZZLE_ENABLE(1); + desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32) | S_008F04_SWIZZLE_ENABLE_GFX6(1); desc[6] = 0; desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) | S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) | @@ -3891,7 +3891,7 @@ radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs, radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2); radeon_emit(cs, scratch_va); - radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) | S_008F04_SWIZZLE_ENABLE(1)); + radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) | S_008F04_SWIZZLE_ENABLE_GFX6(1)); radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE, S_00B860_WAVES(waves) | S_00B860_WAVESIZE(round_up_u32(size_per_wave, 1024))); @@ -4145,7 +4145,7 @@ radv_get_preamble_cs(struct radv_queue *queue, uint32_t scratch_size_per_wave, if (scratch_bo) { uint64_t scratch_va = radv_buffer_get_va(scratch_bo); - uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) | S_008F04_SWIZZLE_ENABLE(1); + uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) | S_008F04_SWIZZLE_ENABLE_GFX6(1); map[0] = scratch_va; map[1] = rsrc1; } @@ -5524,7 +5524,7 @@ radv_init_dcc_control_reg(struct radv_device *device, struct radv_image_view *iv S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) | S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) | S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks) | - S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks); + S_028C78_INDEPENDENT_128B_BLOCKS_GFX10(independent_128b_blocks); } void @@ -5543,7 +5543,7 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff memset(cb, 0, sizeof(*cb)); /* Intensity is implemented as Red, so treat it that way. */ - cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1); + cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1_GFX6(desc->swizzle[3] == PIPE_SWIZZLE_1); va = radv_buffer_get_va(iview->image->bo) + iview->image->offset; @@ -5633,7 +5633,7 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff unsigned log_samples = util_logbase2(iview->image->info.samples); cb->cb_color_attrib |= - S_028C74_NUM_SAMPLES(log_samples) | S_028C74_NUM_FRAGMENTS(log_samples); + S_028C74_NUM_SAMPLES(log_samples) | S_028C74_NUM_FRAGMENTS_GFX6(log_samples); } if (radv_image_has_fmask(iview->image)) { @@ -5673,7 +5673,7 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff ->color_is_int8 = true; #endif cb->cb_color_info = - S_028C70_FORMAT(format) | S_028C70_COMP_SWAP(swap) | S_028C70_BLEND_CLAMP(blend_clamp) | + S_028C70_FORMAT_GFX6(format) | S_028C70_COMP_SWAP(swap) | S_028C70_BLEND_CLAMP(blend_clamp) | S_028C70_BLEND_BYPASS(blend_bypass) | S_028C70_SIMPLE_FLOAT(1) | S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM && ntype != V_028C70_NUMBER_SNORM && ntype != V_028C70_NUMBER_SRGB && format != V_028C70_COLOR_8_24 && @@ -6228,7 +6228,7 @@ radv_init_sampler(struct radv_device *device, struct radv_sampler *sampler, S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) | S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) | S_008F38_MIP_POINT_PRECLAMP(0)); - sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(border_color_ptr) | + sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR_GFX6(border_color_ptr) | S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(border_color))); if (device->physical_device->rad_info.chip_class >= GFX10) { diff --git a/src/amd/vulkan/radv_meta_fast_clear.c b/src/amd/vulkan/radv_meta_fast_clear.c index e8193fdac00..bc6b0aa6bf3 100644 --- a/src/amd/vulkan/radv_meta_fast_clear.c +++ b/src/amd/vulkan/radv_meta_fast_clear.c @@ -373,7 +373,7 @@ create_pipeline(struct radv_device *device, VkShaderModule vs_module_h, VkPipeli }, &(struct radv_graphics_pipeline_create_info){ .use_rectlist = true, - .custom_blend_mode = V_028808_CB_DCC_DECOMPRESS, + .custom_blend_mode = V_028808_CB_DCC_DECOMPRESS_GFX8, }, &device->meta_state.alloc, &device->meta_state.fast_clear_flush.dcc_decompress_pipeline); if (result != VK_SUCCESS) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 35f99172ca9..a469178b196 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -376,23 +376,23 @@ si_translate_blend_factor(VkBlendFactor factor) case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA: return V_028780_BLEND_ONE_MINUS_DST_ALPHA; case VK_BLEND_FACTOR_CONSTANT_COLOR: - return V_028780_BLEND_CONSTANT_COLOR; + return V_028780_BLEND_CONSTANT_COLOR_GFX6; case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR: - return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR; + return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR_GFX6; case VK_BLEND_FACTOR_CONSTANT_ALPHA: - return V_028780_BLEND_CONSTANT_ALPHA; + return V_028780_BLEND_CONSTANT_ALPHA_GFX6; case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA: - return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA; + return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA_GFX6; case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE: return V_028780_BLEND_SRC_ALPHA_SATURATE; case VK_BLEND_FACTOR_SRC1_COLOR: - return V_028780_BLEND_SRC1_COLOR; + return V_028780_BLEND_SRC1_COLOR_GFX6; case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR: - return V_028780_BLEND_INV_SRC1_COLOR; + return V_028780_BLEND_INV_SRC1_COLOR_GFX6; case VK_BLEND_FACTOR_SRC1_ALPHA: - return V_028780_BLEND_SRC1_ALPHA; + return V_028780_BLEND_SRC1_ALPHA_GFX6; case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA: - return V_028780_BLEND_INV_SRC1_ALPHA; + return V_028780_BLEND_INV_SRC1_ALPHA_GFX6; default: return 0; } @@ -5571,7 +5571,7 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf S_028B90_CNT(gs_num_invocations) | S_028B90_ENABLE(gs_num_invocations > 1) | S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state->max_vert_out_per_gs_instance)); - ge_cntl = S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) | + ge_cntl = S_03096C_PRIM_GRP_SIZE_GFX10(ngg_state->max_gsprims) | S_03096C_VERT_GRP_SIZE(ngg_state->enable_vertex_grouping ? ngg_state->hw_max_esverts : 256) | /* 256 = disable vertex grouping */ S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi); @@ -5601,8 +5601,8 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf C_00B21C_CU_EN, 0, &pipeline->device->physical_device->rad_info, (void*)gfx10_set_sh_reg_idx3); ac_set_reg_cu_en(cs, R_00B204_SPI_SHADER_PGM_RSRC4_GS, - S_00B204_CU_EN(0xffff) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_wave64), - C_00B204_CU_EN, 16, &pipeline->device->physical_device->rad_info, + S_00B204_CU_EN_GFX10(0xffff) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_wave64), + C_00B204_CU_EN_GFX10, 16, &pipeline->device->physical_device->rad_info, (void*)gfx10_set_sh_reg_idx3); } else { radeon_set_sh_reg_idx( @@ -5610,7 +5610,7 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf S_00B21C_CU_EN(cu_mask) | S_00B21C_WAVE_LIMIT(0x3F)); radeon_set_sh_reg_idx( pipeline->device->physical_device, cs, R_00B204_SPI_SHADER_PGM_RSRC4_GS, 3, - S_00B204_CU_EN(0xffff) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_wave64)); + S_00B204_CU_EN_GFX10(0xffff) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_wave64)); } uint32_t oversub_pc_lines = late_alloc_wave64 ? pipeline->device->physical_device->rad_info.pc_lines / 4 : 0; @@ -5861,8 +5861,8 @@ radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf C_00B21C_CU_EN, 0, &pipeline->device->physical_device->rad_info, (void*)gfx10_set_sh_reg_idx3); ac_set_reg_cu_en(cs, R_00B204_SPI_SHADER_PGM_RSRC4_GS, - S_00B204_CU_EN(0xffff) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(0), - C_00B204_CU_EN, 16, &pipeline->device->physical_device->rad_info, + S_00B204_CU_EN_GFX10(0xffff) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(0), + C_00B204_CU_EN_GFX10, 16, &pipeline->device->physical_device->rad_info, (void*)gfx10_set_sh_reg_idx3); } else if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) { radeon_set_sh_reg_idx( @@ -5872,7 +5872,7 @@ radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) { radeon_set_sh_reg_idx( pipeline->device->physical_device, cs, R_00B204_SPI_SHADER_PGM_RSRC4_GS, 3, - S_00B204_CU_EN(0xffff) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(0)); + S_00B204_CU_EN_GFX10(0xffff) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(0)); } } @@ -6262,7 +6262,7 @@ gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf *ctx_cs, struct radv_pipeli } radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, - S_03096C_PRIM_GRP_SIZE(primgroup_size) | + S_03096C_PRIM_GRP_SIZE_GFX10(primgroup_size) | S_03096C_VERT_GRP_SIZE(vertgroup_size) | S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ | S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi)); @@ -6540,7 +6540,7 @@ radv_pipeline_init_extra(struct radv_pipeline *pipeline, { if (extra->custom_blend_mode == V_028808_CB_ELIMINATE_FAST_CLEAR || extra->custom_blend_mode == V_028808_CB_FMASK_DECOMPRESS || - extra->custom_blend_mode == V_028808_CB_DCC_DECOMPRESS || + extra->custom_blend_mode == V_028808_CB_DCC_DECOMPRESS_GFX8 || extra->custom_blend_mode == V_028808_CB_RESOLVE) { /* According to the CB spec states, CB_SHADER_MASK should be set to enable writes to all four * channels of MRT0. diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index 20a1b3acaea..ce975885365 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -408,7 +408,7 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs) meta_read_policy = V_02807C_CACHE_LRU_RD; /* cache reads */ } else { meta_write_policy = V_02807C_CACHE_STREAM; /* write combine */ - meta_read_policy = V_02807C_CACHE_NOA; /* don't cache reads */ + meta_read_policy = V_02807C_CACHE_NOA_GFX10; /* don't cache reads */ } radeon_set_context_reg( @@ -416,17 +416,17 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs) S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM) | S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM) | S_02807C_HTILE_WR_POLICY(meta_write_policy) | S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM) | - S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA) | S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA) | + S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_GFX10) | S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_GFX10) | S_02807C_HTILE_RD_POLICY(meta_read_policy)); radeon_set_context_reg( cs, R_028410_CB_RMI_GL2_CACHE_CONTROL, S_028410_CMASK_WR_POLICY(meta_write_policy) | S_028410_FMASK_WR_POLICY(meta_write_policy) | - S_028410_DCC_WR_POLICY(meta_write_policy) | - S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM) | + S_028410_DCC_WR_POLICY_GFX10(meta_write_policy) | + S_028410_COLOR_WR_POLICY_GFX10(V_028410_CACHE_STREAM) | S_028410_CMASK_RD_POLICY(meta_read_policy) | S_028410_FMASK_RD_POLICY(meta_read_policy) | S_028410_DCC_RD_POLICY(meta_read_policy) | - S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA)); + S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_GFX10)); radeon_set_context_reg(cs, R_028428_CB_COVERAGE_OUT_CONTROL, 0); radeon_set_sh_reg_seq(cs, R_00B0C8_SPI_SHADER_USER_ACCUM_PS_0, 4); diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c index e64009c64b0..73c1344a0dc 100644 --- a/src/gallium/drivers/radeonsi/si_compute.c +++ b/src/gallium/drivers/radeonsi/si_compute.c @@ -580,7 +580,7 @@ static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx, uint32_t scratch_dword0 = scratch_va & 0xffffffff; uint32_t scratch_dword1 = - S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) | S_008F04_SWIZZLE_ENABLE(1); + S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) | S_008F04_SWIZZLE_ENABLE_GFX6(1); /* Disable address clamping */ uint32_t scratch_dword2 = 0xffffffff; diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index 6dba441cb87..08ab5b538ef 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -1533,7 +1533,7 @@ void si_set_ring_buffer(struct si_context *sctx, uint slot, struct pipe_resource uint32_t *desc = descs->list + slot * 4; desc[0] = va; desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride) | - S_008F04_SWIZZLE_ENABLE(swizzle); + S_008F04_SWIZZLE_ENABLE_GFX6(swizzle); desc[2] = num_records; desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) | S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) | diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index b45bc77522a..9399cd98782 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -862,7 +862,7 @@ static bool si_get_external_symbol(void *data, const char *name, uint64_t *value } if (!strcmp(scratch_rsrc_dword1_symbol, name)) { /* Enable scratch coalescing. */ - *value = S_008F04_BASE_ADDRESS_HI(*scratch_va >> 32) | S_008F04_SWIZZLE_ENABLE(1); + *value = S_008F04_BASE_ADDRESS_HI(*scratch_va >> 32) | S_008F04_SWIZZLE_ENABLE_GFX6(1); return true; } diff --git a/src/gallium/drivers/radeonsi/si_shader_llvm_gs.c b/src/gallium/drivers/radeonsi/si_shader_llvm_gs.c index 9362499b97e..90e48dca498 100644 --- a/src/gallium/drivers/radeonsi/si_shader_llvm_gs.c +++ b/src/gallium/drivers/radeonsi/si_shader_llvm_gs.c @@ -327,7 +327,7 @@ void si_preload_esgs_ring(struct si_shader_context *ctx) LLVMValueRef desc3 = LLVMBuildExtractElement(builder, ctx->esgs_ring, LLVMConstInt(ctx->ac.i32, 3, 0), ""); desc1 = LLVMBuildOr(builder, desc1, LLVMConstInt(ctx->ac.i32, - S_008F04_SWIZZLE_ENABLE(1), 0), ""); + S_008F04_SWIZZLE_ENABLE_GFX6(1), 0), ""); desc3 = LLVMBuildOr(builder, desc3, LLVMConstInt(ctx->ac.i32, S_008F0C_ELEMENT_SIZE(1) | S_008F0C_INDEX_STRIDE(3) | @@ -400,7 +400,7 @@ void si_preload_gs_rings(struct si_shader_context *ctx) tmp = LLVMBuildExtractElement(builder, ring, ctx->ac.i32_1, ""); tmp = LLVMBuildOr( builder, tmp, - LLVMConstInt(ctx->ac.i32, S_008F04_STRIDE(stride) | S_008F04_SWIZZLE_ENABLE(1), 0), ""); + LLVMConstInt(ctx->ac.i32, S_008F04_STRIDE(stride) | S_008F04_SWIZZLE_ENABLE_GFX6(1), 0), ""); ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->ac.i32_1, ""); ring = LLVMBuildInsertElement(builder, ring, LLVMConstInt(ctx->ac.i32, num_records, 0), LLVMConstInt(ctx->ac.i32, 2, 0), ""); diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 6e77da76c8b..f9e0a86fe10 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -144,13 +144,13 @@ static void si_emit_cb_render_state(struct si_context *sctx) continue; } - format = G_028C70_FORMAT(surf->cb_color_info); + format = G_028C70_FORMAT_GFX6(surf->cb_color_info); swap = G_028C70_COMP_SWAP(surf->cb_color_info); spi_format = (spi_shader_col_format >> (i * 4)) & 0xf; colormask = (cb_target_mask >> (i * 4)) & 0xf; /* Set if RGB and A are present. */ - has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib); + has_alpha = !G_028C74_FORCE_DST_ALPHA_1_GFX6(surf->cb_color_attrib); if (format == V_028C70_COLOR_8 || format == V_028C70_COLOR_16 || format == V_028C70_COLOR_32) @@ -305,9 +305,9 @@ static uint32_t si_translate_blend_factor(int blend_fact) case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE: return V_028780_BLEND_SRC_ALPHA_SATURATE; case PIPE_BLENDFACTOR_CONST_COLOR: - return V_028780_BLEND_CONSTANT_COLOR; + return V_028780_BLEND_CONSTANT_COLOR_GFX6; case PIPE_BLENDFACTOR_CONST_ALPHA: - return V_028780_BLEND_CONSTANT_ALPHA; + return V_028780_BLEND_CONSTANT_ALPHA_GFX6; case PIPE_BLENDFACTOR_ZERO: return V_028780_BLEND_ZERO; case PIPE_BLENDFACTOR_INV_SRC_COLOR: @@ -319,17 +319,17 @@ static uint32_t si_translate_blend_factor(int blend_fact) case PIPE_BLENDFACTOR_INV_DST_COLOR: return V_028780_BLEND_ONE_MINUS_DST_COLOR; case PIPE_BLENDFACTOR_INV_CONST_COLOR: - return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR; + return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR_GFX6; case PIPE_BLENDFACTOR_INV_CONST_ALPHA: - return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA; + return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA_GFX6; case PIPE_BLENDFACTOR_SRC1_COLOR: - return V_028780_BLEND_SRC1_COLOR; + return V_028780_BLEND_SRC1_COLOR_GFX6; case PIPE_BLENDFACTOR_SRC1_ALPHA: - return V_028780_BLEND_SRC1_ALPHA; + return V_028780_BLEND_SRC1_ALPHA_GFX6; case PIPE_BLENDFACTOR_INV_SRC1_COLOR: - return V_028780_BLEND_INV_SRC1_COLOR; + return V_028780_BLEND_INV_SRC1_COLOR_GFX6; case PIPE_BLENDFACTOR_INV_SRC1_ALPHA: - return V_028780_BLEND_INV_SRC1_ALPHA; + return V_028780_BLEND_INV_SRC1_ALPHA_GFX6; default: PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact); assert(0); @@ -2492,7 +2492,7 @@ static void si_initialize_color_surface(struct si_context *sctx, struct si_surfa } color_info = - S_028C70_FORMAT(format) | S_028C70_COMP_SWAP(swap) | S_028C70_BLEND_CLAMP(blend_clamp) | + S_028C70_FORMAT_GFX6(format) | S_028C70_COMP_SWAP(swap) | S_028C70_BLEND_CLAMP(blend_clamp) | S_028C70_BLEND_BYPASS(blend_bypass) | S_028C70_SIMPLE_FLOAT(1) | S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM && ntype != V_028C70_NUMBER_SNORM && ntype != V_028C70_NUMBER_SRGB && format != V_028C70_COLOR_8_24 && @@ -2500,14 +2500,14 @@ static void si_initialize_color_surface(struct si_context *sctx, struct si_surfa S_028C70_NUMBER_TYPE(ntype) | S_028C70_ENDIAN(endian); /* Intensity is implemented as Red, so treat it that way. */ - color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 || - util_format_is_intensity(surf->base.format)); + color_attrib = S_028C74_FORCE_DST_ALPHA_1_GFX6(desc->swizzle[3] == PIPE_SWIZZLE_1 || + util_format_is_intensity(surf->base.format)); if (tex->buffer.b.b.nr_samples > 1) { unsigned log_samples = util_logbase2(tex->buffer.b.b.nr_samples); unsigned log_fragments = util_logbase2(tex->buffer.b.b.nr_storage_samples); - color_attrib |= S_028C74_NUM_SAMPLES(log_samples) | S_028C74_NUM_FRAGMENTS(log_fragments); + color_attrib |= S_028C74_NUM_SAMPLES(log_samples) | S_028C74_NUM_FRAGMENTS_GFX6(log_fragments); if (tex->surface.fmask_offset) { color_info |= S_028C70_COMPRESSION(1); @@ -2533,7 +2533,7 @@ static void si_initialize_color_surface(struct si_context *sctx, struct si_surfa S_028C78_MAX_COMPRESSED_BLOCK_SIZE(tex->surface.u.gfx9.color.dcc.max_compressed_block_size) | S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) | S_028C78_INDEPENDENT_64B_BLOCKS(tex->surface.u.gfx9.color.dcc.independent_64B_blocks) | - S_028C78_INDEPENDENT_128B_BLOCKS(tex->surface.u.gfx9.color.dcc.independent_128B_blocks); + S_028C78_INDEPENDENT_128B_BLOCKS_GFX10(tex->surface.u.gfx9.color.dcc.independent_128B_blocks); } else if (sctx->chip_class >= GFX8) { unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B; @@ -3117,7 +3117,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx) cb = (struct si_surface *)state->cbufs[i]; if (!cb) { radeon_set_context_reg(R_028C70_CB_COLOR0_INFO + i * 0x3C, - S_028C70_FORMAT(V_028C70_COLOR_INVALID)); + S_028C70_FORMAT_GFX6(V_028C70_COLOR_INVALID)); continue; } @@ -4543,7 +4543,7 @@ static uint32_t si_translate_border_color(struct si_context *sctx, sctx->border_color_count++; } - return S_008F3C_BORDER_COLOR_PTR(i) | + return S_008F3C_BORDER_COLOR_PTR_GFX6(i) | S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER); } @@ -5276,7 +5276,7 @@ void si_init_state_functions(struct si_context *sctx) sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS); sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR); - sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS); + sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS_GFX8); sctx->b.set_clip_state = si_set_clip_state; sctx->b.set_stencil_ref = si_set_stencil_ref; @@ -5616,7 +5616,7 @@ void si_init_cs_preamble_state(struct si_context *sctx, bool uses_reg_shadowing) meta_read_policy = V_02807C_CACHE_LRU_RD; /* cache reads */ } else { meta_write_policy = V_02807C_CACHE_STREAM; /* write combine */ - meta_read_policy = V_02807C_CACHE_NOA; /* don't cache reads */ + meta_read_policy = V_02807C_CACHE_NOA_GFX10; /* don't cache reads */ } si_pm4_set_reg(pm4, R_02807C_DB_RMI_L2_CACHE_CONTROL, @@ -5624,18 +5624,18 @@ void si_init_cs_preamble_state(struct si_context *sctx, bool uses_reg_shadowing) S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM) | S_02807C_HTILE_WR_POLICY(meta_write_policy) | S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM) | - S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA) | - S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA) | + S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_GFX10) | + S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_GFX10) | S_02807C_HTILE_RD_POLICY(meta_read_policy)); si_pm4_set_reg(pm4, R_028410_CB_RMI_GL2_CACHE_CONTROL, S_028410_CMASK_WR_POLICY(meta_write_policy) | S_028410_FMASK_WR_POLICY(V_028410_CACHE_STREAM) | - S_028410_DCC_WR_POLICY(meta_write_policy) | - S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM) | + S_028410_DCC_WR_POLICY_GFX10(meta_write_policy) | + S_028410_COLOR_WR_POLICY_GFX10(V_028410_CACHE_STREAM) | S_028410_CMASK_RD_POLICY(meta_read_policy) | - S_028410_FMASK_RD_POLICY(V_028410_CACHE_NOA) | + S_028410_FMASK_RD_POLICY(V_028410_CACHE_NOA_GFX10) | S_028410_DCC_RD_POLICY(meta_read_policy) | - S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA)); + S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_GFX10)); si_pm4_set_reg(pm4, R_028428_CB_COVERAGE_OUT_CONTROL, 0); si_pm4_set_reg(pm4, R_028A98_VGT_DRAW_PAYLOAD_CNTL, 0); diff --git a/src/gallium/drivers/radeonsi/si_state_draw.cpp b/src/gallium/drivers/radeonsi/si_state_draw.cpp index 8bdf945ae90..014e20f8741 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.cpp +++ b/src/gallium/drivers/radeonsi/si_state_draw.cpp @@ -1216,7 +1216,7 @@ static void gfx10_emit_ge_cntl(struct si_context *sctx, unsigned num_patches) if (NGG) { if (HAS_TESS) { - ge_cntl = S_03096C_PRIM_GRP_SIZE(num_patches) | + ge_cntl = S_03096C_PRIM_GRP_SIZE_GFX10(num_patches) | S_03096C_VERT_GRP_SIZE(0) | S_03096C_BREAK_WAVE_AT_EOI(key.u.tess_uses_prim_id); } else { @@ -1238,7 +1238,8 @@ static void gfx10_emit_ge_cntl(struct si_context *sctx, unsigned num_patches) vertgroup_size = 0; } - ge_cntl = S_03096C_PRIM_GRP_SIZE(primgroup_size) | S_03096C_VERT_GRP_SIZE(vertgroup_size) | + ge_cntl = S_03096C_PRIM_GRP_SIZE_GFX10(primgroup_size) | + S_03096C_VERT_GRP_SIZE(vertgroup_size) | S_03096C_BREAK_WAVE_AT_EOI(key.u.uses_tess && key.u.tess_uses_prim_id); } diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.cpp b/src/gallium/drivers/radeonsi/si_state_shaders.cpp index 249cd5ff687..d6ca87b73c6 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.cpp +++ b/src/gallium/drivers/radeonsi/si_state_shaders.cpp @@ -968,7 +968,7 @@ static void si_emit_shader_gs(struct si_context *sctx) if (sctx->chip_class >= GFX10) { ac_set_reg_cu_en(&sctx->gfx_cs, R_00B204_SPI_SHADER_PGM_RSRC4_GS, shader->ctx_reg.gs.spi_shader_pgm_rsrc4_gs, - C_00B204_CU_EN, 16, &sctx->screen->info, + C_00B204_CU_EN_GFX10, 16, &sctx->screen->info, (void (*)(void*, unsigned, uint32_t)) (sctx->chip_class >= GFX10 ? radeon_set_sh_reg_idx3_func : radeon_set_sh_reg_func)); sctx->tracked_regs.reg_saved &= ~BITFIELD64_BIT(SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS); @@ -1098,7 +1098,7 @@ static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader) shader->ctx_reg.gs.spi_shader_pgm_rsrc3_gs = S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F); shader->ctx_reg.gs.spi_shader_pgm_rsrc4_gs = - S_00B204_CU_EN(0xffff) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(0); + S_00B204_CU_EN_GFX10(0xffff) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(0); shader->ctx_reg.gs.vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) | @@ -1194,7 +1194,7 @@ static void gfx10_emit_shader_ngg_tail(struct si_context *sctx, struct si_shader (sctx->chip_class >= GFX10 ? radeon_set_sh_reg_idx3_func : radeon_set_sh_reg_func)); ac_set_reg_cu_en(&sctx->gfx_cs, R_00B204_SPI_SHADER_PGM_RSRC4_GS, shader->ctx_reg.ngg.spi_shader_pgm_rsrc4_gs, - C_00B204_CU_EN, 16, &sctx->screen->info, + C_00B204_CU_EN_GFX10, 16, &sctx->screen->info, (void (*)(void*, unsigned, uint32_t)) (sctx->chip_class >= GFX10 ? radeon_set_sh_reg_idx3_func : radeon_set_sh_reg_func)); sctx->tracked_regs.reg_saved &= ~BITFIELD64_BIT(SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS) & @@ -1404,7 +1404,7 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader shader->ctx_reg.ngg.spi_shader_pgm_rsrc3_gs = S_00B21C_CU_EN(cu_mask) | S_00B21C_WAVE_LIMIT(0x3F); shader->ctx_reg.ngg.spi_shader_pgm_rsrc4_gs = - S_00B204_CU_EN(0xffff) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_wave64); + S_00B204_CU_EN_GFX10(0xffff) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_wave64); nparams = MAX2(shader->info.nr_param_exports, 1); shader->ctx_reg.ngg.spi_vs_out_config = @@ -1477,7 +1477,7 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader shader->ctx_reg.ngg.ge_pc_alloc = S_030980_OVERSUB_EN(oversub_pc_lines > 0) | S_030980_NUM_PC_LINES(oversub_pc_lines - 1); - shader->ge_cntl = S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) | + shader->ge_cntl = S_03096C_PRIM_GRP_SIZE_GFX10(shader->ngg.max_gsprims) | S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts) | S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);