From 97c7d5113db0ee7297c8674f5b608ad729408b02 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Thu, 21 Mar 2024 11:02:41 -0700 Subject: [PATCH] intel/brw: Use correct execution pipe for lowering SEL on DF This is a float operation, let's keep it on the float pipe. Fixes: ea423aba1b45 ("intel/brw: Split out 64-bit lowering from algebraic optimizations") Reviewed-by: Lionel Landwerlin Part-of: --- src/intel/compiler/brw_fs_lower.cpp | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/src/intel/compiler/brw_fs_lower.cpp b/src/intel/compiler/brw_fs_lower.cpp index ae90f106fa6..17c956bb0b1 100644 --- a/src/intel/compiler/brw_fs_lower.cpp +++ b/src/intel/compiler/brw_fs_lower.cpp @@ -637,17 +637,20 @@ brw_fs_lower_alu_restrictions(fs_visitor &s) assert(inst->conditional_mod == BRW_CONDITIONAL_NONE); const brw::fs_builder ibld(&s, block, inst); + enum brw_reg_type type = + brw_reg_type_from_bit_size(32, inst->dst.type); + if (!inst->is_partial_write()) ibld.emit_undef_for_dst(inst); set_predicate(inst->predicate, - ibld.SEL(subscript(inst->dst, BRW_REGISTER_TYPE_UD, 0), - subscript(inst->src[0], BRW_REGISTER_TYPE_UD, 0), - subscript(inst->src[1], BRW_REGISTER_TYPE_UD, 0))); + ibld.SEL(subscript(inst->dst, type, 0), + subscript(inst->src[0], type, 0), + subscript(inst->src[1], type, 0))); set_predicate(inst->predicate, - ibld.SEL(subscript(inst->dst, BRW_REGISTER_TYPE_UD, 1), - subscript(inst->src[0], BRW_REGISTER_TYPE_UD, 1), - subscript(inst->src[1], BRW_REGISTER_TYPE_UD, 1))); + ibld.SEL(subscript(inst->dst, type, 1), + subscript(inst->src[0], type, 1), + subscript(inst->src[1], type, 1))); inst->remove(block); progress = true;