From 961c72d666f33853e526819f3d0d43975cf6b56b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Thu, 22 Aug 2024 15:47:57 -0400 Subject: [PATCH] radeonsi: remove SI_OP_SYNC_CPDMA_BEFORE, always sync CP DMA We want barriers to only consider compute as a possibility, and CP DMA has to work with that, which means barriers can't have code specific to CP DMA. Always executing the CP DMA sync seems acceptable because CP DMA operations are usually small, and CP DMA is almost never used on GFX10+. Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/gallium/drivers/radeonsi/si_compute_blit.c | 3 +-- src/gallium/drivers/radeonsi/si_cp_dma.c | 2 +- src/gallium/drivers/radeonsi/si_pipe.h | 5 ++--- 3 files changed, 4 insertions(+), 6 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_compute_blit.c b/src/gallium/drivers/radeonsi/si_compute_blit.c index 6146592444e..5fcc9e54bc4 100644 --- a/src/gallium/drivers/radeonsi/si_compute_blit.c +++ b/src/gallium/drivers/radeonsi/si_compute_blit.c @@ -28,8 +28,7 @@ static void si_improve_sync_flags(struct si_context *sctx, struct pipe_resource if (si_is_buffer_idle(sctx, si_resource(dst), RADEON_USAGE_READWRITE) && (!src || si_is_buffer_idle(sctx, si_resource(src), RADEON_USAGE_WRITE))) { /* Idle buffers don't have to sync. */ - *flags &= ~(SI_OP_SYNC_GE_BEFORE | SI_OP_SYNC_PS_BEFORE | SI_OP_SYNC_CS_BEFORE | - SI_OP_SYNC_CPDMA_BEFORE); + *flags &= ~(SI_OP_SYNC_GE_BEFORE | SI_OP_SYNC_PS_BEFORE | SI_OP_SYNC_CS_BEFORE); return; } diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/gallium/drivers/radeonsi/si_cp_dma.c index 60331bb20ec..b032f144cd8 100644 --- a/src/gallium/drivers/radeonsi/si_cp_dma.c +++ b/src/gallium/drivers/radeonsi/si_cp_dma.c @@ -128,7 +128,7 @@ static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource *dst if (*is_first && sctx->flags) si_emit_cache_flush_direct(sctx); - if (user_flags & SI_OP_SYNC_CPDMA_BEFORE && *is_first && !(*packet_flags & CP_DMA_CLEAR)) + if (*is_first && !(*packet_flags & CP_DMA_CLEAR)) *packet_flags |= CP_DMA_RAW_WAIT; *is_first = false; diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index 8b44fabc85f..fd9f04997ae 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -1461,15 +1461,14 @@ void si_destroy_compute(struct si_compute *program); /* si_compute_blit.c */ #define SI_OP_SYNC_CS_BEFORE (1 << 0) #define SI_OP_SYNC_PS_BEFORE (1 << 1) -#define SI_OP_SYNC_CPDMA_BEFORE (1 << 2) /* only affects CP DMA calls */ -#define SI_OP_SYNC_BEFORE (SI_OP_SYNC_CS_BEFORE | SI_OP_SYNC_PS_BEFORE | SI_OP_SYNC_CPDMA_BEFORE) +#define SI_OP_SYNC_GE_BEFORE (1 << 2) /* only sync VS, TCS, TES, GS */ +#define SI_OP_SYNC_BEFORE (SI_OP_SYNC_CS_BEFORE | SI_OP_SYNC_PS_BEFORE) #define SI_OP_SYNC_AFTER (1 << 3) #define SI_OP_SYNC_BEFORE_AFTER (SI_OP_SYNC_BEFORE | SI_OP_SYNC_AFTER) #define SI_OP_SKIP_CACHE_INV_BEFORE (1 << 4) /* don't invalidate caches */ #define SI_OP_CS_IMAGE (1 << 5) #define SI_OP_CS_RENDER_COND_ENABLE (1 << 6) /* gap */ -#define SI_OP_SYNC_GE_BEFORE (1 << 8) /* only sync VS, TCS, TES, GS */ /* Only for si_compute_blit: */ #define SI_OP_FAIL_IF_SLOW (1 << 9) #define SI_OP_IS_NESTED (1 << 10)