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radv: export implicit primitive ID in NIR for legacy VS or TES

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It's implicit for VS or TES, while it's required for GS or MS.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16404>
This commit is contained in:
Samuel Pitoiset
2022-05-10 19:48:32 +02:00
committed by Marge Bot
parent d711e9813c
commit 95d4e5435b
4 changed files with 42 additions and 25 deletions
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src/amd/compiler/aco_instruction_selection.cpp
+3 -10
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@@ -8872,6 +8872,9 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr)
* even if there is no SW GS. */
bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.gs_prim_id));
break;
} else if (ctx->shader->info.stage == MESA_SHADER_VERTEX) {
bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.vs_prim_id));
break;
}
unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
}
@@ -10632,16 +10635,6 @@ create_vs_exports(isel_context* ctx)
assert(outinfo);
ctx->block->kind |= block_kind_export_end;
if (outinfo->export_prim_id && ctx->stage.hw != HWStage::NGG) {
ctx->outputs.mask[VARYING_SLOT_PRIMITIVE_ID] |= 0x1;
if (ctx->stage.has(SWStage::TES))
ctx->outputs.temps[VARYING_SLOT_PRIMITIVE_ID * 4u] =
get_arg(ctx, ctx->args->ac.tes_patch_id);
else
ctx->outputs.temps[VARYING_SLOT_PRIMITIVE_ID * 4u] =
get_arg(ctx, ctx->args->ac.vs_prim_id);
}
/* Hardware requires position data to always be exported, even if the
* application did not write gl_Position.
*/