diff --git a/src/amd/common/ac_shadowed_regs.c b/src/amd/common/ac_shadowed_regs.c
index 538c5f8e483..ecbba660025 100644
--- a/src/amd/common/ac_shadowed_regs.c
+++ b/src/amd/common/ac_shadowed_regs.c
@@ -363,8 +363,8 @@ static const struct ac_reg_range Nv10UserConfigShadowRange[] = {
       4,
    },
    {
-      R_030904_VGT_GSVS_RING_SIZE_UMD,
-      R_030908_VGT_PRIMITIVE_TYPE - R_030904_VGT_GSVS_RING_SIZE_UMD + 4,
+      R_030904_VGT_GSVS_RING_SIZE,
+      R_030908_VGT_PRIMITIVE_TYPE - R_030904_VGT_GSVS_RING_SIZE + 4,
    },
    {
       R_030964_GE_MAX_VTX_INDX,
@@ -376,11 +376,11 @@ static const struct ac_reg_range Nv10UserConfigShadowRange[] = {
    },
    {
       R_030934_VGT_NUM_INSTANCES,
-      R_030940_VGT_TF_MEMORY_BASE_UMD - R_030934_VGT_NUM_INSTANCES + 4,
+      R_030940_VGT_TF_MEMORY_BASE - R_030934_VGT_NUM_INSTANCES + 4,
    },
    {
       R_03097C_GE_STEREO_CNTL,
-      R_030984_VGT_TF_MEMORY_BASE_HI_UMD - R_03097C_GE_STEREO_CNTL + 4,
+      R_030984_VGT_TF_MEMORY_BASE_HI - R_03097C_GE_STEREO_CNTL + 4,
    },
    {
       R_03096C_GE_CNTL,
@@ -691,8 +691,8 @@ static const struct ac_reg_range Gfx103UserConfigShadowRange[] = {
       4,
    },
    {
-      R_030904_VGT_GSVS_RING_SIZE_UMD,
-      R_030908_VGT_PRIMITIVE_TYPE - R_030904_VGT_GSVS_RING_SIZE_UMD + 4,
+      R_030904_VGT_GSVS_RING_SIZE,
+      R_030908_VGT_PRIMITIVE_TYPE - R_030904_VGT_GSVS_RING_SIZE + 4,
    },
    {
       R_030964_GE_MAX_VTX_INDX,
@@ -704,11 +704,11 @@ static const struct ac_reg_range Gfx103UserConfigShadowRange[] = {
    },
    {
       R_030934_VGT_NUM_INSTANCES,
-      R_030940_VGT_TF_MEMORY_BASE_UMD - R_030934_VGT_NUM_INSTANCES + 4,
+      R_030940_VGT_TF_MEMORY_BASE - R_030934_VGT_NUM_INSTANCES + 4,
    },
    {
       R_03097C_GE_STEREO_CNTL,
-      R_030984_VGT_TF_MEMORY_BASE_HI_UMD - R_03097C_GE_STEREO_CNTL + 4,
+      R_030984_VGT_TF_MEMORY_BASE_HI - R_03097C_GE_STEREO_CNTL + 4,
    },
    {
       R_03096C_GE_CNTL,
diff --git a/src/amd/registers/gfx10.json b/src/amd/registers/gfx10.json
index 2de91f5e174..53edb48c7af 100644
--- a/src/amd/registers/gfx10.json
+++ b/src/amd/registers/gfx10.json
@@ -8045,12 +8045,12 @@
   {
    "chips": ["gfx10"],
    "map": {"at": 198912, "to": "mm"},
-   "name": "VGT_ESGS_RING_SIZE_UMD"
+   "name": "VGT_ESGS_RING_SIZE"
   },
   {
    "chips": ["gfx10"],
    "map": {"at": 198916, "to": "mm"},
-   "name": "VGT_GSVS_RING_SIZE_UMD"
+   "name": "VGT_GSVS_RING_SIZE"
   },
   {
    "chips": ["gfx10"],
@@ -8113,19 +8113,19 @@
   {
    "chips": ["gfx10"],
    "map": {"at": 198968, "to": "mm"},
-   "name": "VGT_TF_RING_SIZE_UMD",
-   "type_ref": "VGT_TF_RING_SIZE_UMD"
+   "name": "VGT_TF_RING_SIZE",
+   "type_ref": "VGT_TF_RING_SIZE"
   },
   {
    "chips": ["gfx10"],
    "map": {"at": 198972, "to": "mm"},
-   "name": "VGT_HS_OFFCHIP_PARAM_UMD",
-   "type_ref": "VGT_HS_OFFCHIP_PARAM_UMD"
+   "name": "VGT_HS_OFFCHIP_PARAM",
+   "type_ref": "VGT_HS_OFFCHIP_PARAM"
   },
   {
    "chips": ["gfx10"],
    "map": {"at": 198976, "to": "mm"},
-   "name": "VGT_TF_MEMORY_BASE_UMD"
+   "name": "VGT_TF_MEMORY_BASE"
   },
   {
    "chips": ["gfx10"],
@@ -8217,7 +8217,7 @@
   {
    "chips": ["gfx10"],
    "map": {"at": 199044, "to": "mm"},
-   "name": "VGT_TF_MEMORY_BASE_HI_UMD",
+   "name": "VGT_TF_MEMORY_BASE_HI",
    "type_ref": "DB_Z_READ_BASE_HI"
   },
   {
@@ -15161,7 +15161,7 @@
     {"bits": [0, 7], "name": "REUSE_DEPTH"}
    ]
   },
-  "VGT_HS_OFFCHIP_PARAM_UMD": {
+  "VGT_HS_OFFCHIP_PARAM": {
    "fields": [
     {"bits": [0, 8], "name": "OFFCHIP_BUFFERING"},
     {"bits": [9, 10], "enum_ref": "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY", "name": "OFFCHIP_GRANULARITY"}
@@ -15285,7 +15285,7 @@
     {"bits": [23, 25], "name": "MTYPE"}
    ]
   },
-  "VGT_TF_RING_SIZE_UMD": {
+  "VGT_TF_RING_SIZE": {
    "fields": [
     {"bits": [0, 15], "name": "SIZE"}
    ]
diff --git a/src/amd/registers/gfx103.json b/src/amd/registers/gfx103.json
index bcc9702149f..bd309155b83 100644
--- a/src/amd/registers/gfx103.json
+++ b/src/amd/registers/gfx103.json
@@ -7456,12 +7456,12 @@
   {
    "chips": ["gfx103"],
    "map": {"at": 198912, "to": "mm"},
-   "name": "VGT_ESGS_RING_SIZE_UMD"
+   "name": "VGT_ESGS_RING_SIZE"
   },
   {
    "chips": ["gfx103"],
    "map": {"at": 198916, "to": "mm"},
-   "name": "VGT_GSVS_RING_SIZE_UMD"
+   "name": "VGT_GSVS_RING_SIZE"
   },
   {
    "chips": ["gfx103"],
@@ -7524,19 +7524,19 @@
   {
    "chips": ["gfx103"],
    "map": {"at": 198968, "to": "mm"},
-   "name": "VGT_TF_RING_SIZE_UMD",
-   "type_ref": "VGT_TF_RING_SIZE_UMD"
+   "name": "VGT_TF_RING_SIZE",
+   "type_ref": "VGT_TF_RING_SIZE"
   },
   {
    "chips": ["gfx103"],
    "map": {"at": 198972, "to": "mm"},
-   "name": "VGT_HS_OFFCHIP_PARAM_UMD",
-   "type_ref": "VGT_HS_OFFCHIP_PARAM_UMD"
+   "name": "VGT_HS_OFFCHIP_PARAM",
+   "type_ref": "VGT_HS_OFFCHIP_PARAM"
   },
   {
    "chips": ["gfx103"],
    "map": {"at": 198976, "to": "mm"},
-   "name": "VGT_TF_MEMORY_BASE_UMD"
+   "name": "VGT_TF_MEMORY_BASE"
   },
   {
    "chips": ["gfx103"],
@@ -7628,7 +7628,7 @@
   {
    "chips": ["gfx103"],
    "map": {"at": 199044, "to": "mm"},
-   "name": "VGT_TF_MEMORY_BASE_HI_UMD",
+   "name": "VGT_TF_MEMORY_BASE_HI",
    "type_ref": "DB_Z_READ_BASE_HI"
   },
   {
@@ -14996,7 +14996,7 @@
     {"bits": [0, 7], "name": "REUSE_DEPTH"}
    ]
   },
-  "VGT_HS_OFFCHIP_PARAM_UMD": {
+  "VGT_HS_OFFCHIP_PARAM": {
    "fields": [
     {"bits": [0, 9], "name": "OFFCHIP_BUFFERING"},
     {"bits": [10, 11], "enum_ref": "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY", "name": "OFFCHIP_GRANULARITY"}
@@ -15127,7 +15127,7 @@
     {"bits": [23, 25], "name": "MTYPE"}
    ]
   },
-  "VGT_TF_RING_SIZE_UMD": {
+  "VGT_TF_RING_SIZE": {
    "fields": [
     {"bits": [0, 15], "name": "SIZE"}
    ]
diff --git a/src/amd/registers/parse_kernel_headers.py b/src/amd/registers/parse_kernel_headers.py
index 7920af8259a..1d6a6306cf8 100644
--- a/src/amd/registers/parse_kernel_headers.py
+++ b/src/amd/registers/parse_kernel_headers.py
@@ -683,6 +683,10 @@ def generate_json(gfx_version, amd_headers_path):
             assert idx < len(base_offsets)
             offset += int(base_offsets[idx], 0) * 4
 
+        # Remove the _UMD suffix because it was mistakenly added to indicate it's for a User-Mode Driver
+        if name[-4:] == '_UMD':
+            name = name[:-4]
+
         # Only accept writeable registers and debug registers
         if register_filter(gfx_version, name, offset, offset in added_offsets):
             regs[name] = {
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index a85c7db68a0..7044f728a8d 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -3791,7 +3791,7 @@ radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
       radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE, tf_va >> 8);
 
       if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
-         radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
+         radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI,
                                 S_030984_BASE_HI(tf_va >> 40));
       } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
          radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI, S_030944_BASE_HI(tf_va >> 40));
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.cpp b/src/gallium/drivers/radeonsi/si_state_shaders.cpp
index 8a7c07b7ba1..f5282da74aa 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.cpp
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.cpp
@@ -4147,7 +4147,7 @@ void si_init_tess_factor_ring(struct si_context *sctx)
                              S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
       radeon_set_uconfig_reg(R_030940_VGT_TF_MEMORY_BASE, factor_va >> 8);
       if (sctx->chip_class >= GFX10) {
-         radeon_set_uconfig_reg(R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
+         radeon_set_uconfig_reg(R_030984_VGT_TF_MEMORY_BASE_HI,
                                 S_030984_BASE_HI(factor_va >> 40));
       } else if (sctx->chip_class == GFX9) {
          radeon_set_uconfig_reg(R_030944_VGT_TF_MEMORY_BASE_HI,
@@ -4168,7 +4168,7 @@ void si_init_tess_factor_ring(struct si_context *sctx)
                      S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
       si_pm4_set_reg(sctx->cs_preamble_state, R_030940_VGT_TF_MEMORY_BASE, factor_va >> 8);
       if (sctx->chip_class >= GFX10)
-         si_pm4_set_reg(sctx->cs_preamble_state, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
+         si_pm4_set_reg(sctx->cs_preamble_state, R_030984_VGT_TF_MEMORY_BASE_HI,
                         S_030984_BASE_HI(factor_va >> 40));
       else if (sctx->chip_class == GFX9)
          si_pm4_set_reg(sctx->cs_preamble_state, R_030944_VGT_TF_MEMORY_BASE_HI,