From 95819663b71cff2977849d84a7dc70f62ed2a262 Mon Sep 17 00:00:00 2001 From: Rhys Perry Date: Mon, 23 Nov 2020 13:05:58 +0000 Subject: [PATCH] nir: allow 5 component vectors These will be useful for sparse texture instructions and image load intrinsics. Signed-off-by: Rhys Perry Reviewed-by: Jason Ekstrand Part-of: --- src/compiler/nir/nir.h | 4 +++- src/compiler/nir/nir_builder.h | 3 +++ src/compiler/nir/nir_gather_ssa_types.c | 1 + src/compiler/nir/nir_lower_alu_to_scalar.c | 1 + src/compiler/nir/nir_lower_bool_to_bitsize.c | 2 ++ src/compiler/nir/nir_lower_bool_to_float.c | 1 + src/compiler/nir/nir_lower_bool_to_int32.c | 1 + src/compiler/nir/nir_opcodes.py | 17 +++++++++++++++-- src/compiler/nir/nir_opt_peephole_select.c | 1 + src/compiler/nir/nir_print.c | 2 +- 10 files changed, 29 insertions(+), 4 deletions(-) diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index 47602471557..414943aa6b4 100644 --- a/src/compiler/nir/nir.h +++ b/src/compiler/nir/nir.h @@ -72,7 +72,7 @@ static inline bool nir_num_components_valid(unsigned num_components) { return (num_components >= 1 && - num_components <= 4) || + num_components <= 5) || num_components == 8 || num_components == 16; } @@ -1210,6 +1210,7 @@ nir_op_vec(unsigned components) case 2: return nir_op_vec2; case 3: return nir_op_vec3; case 4: return nir_op_vec4; + case 5: return nir_op_vec5; case 8: return nir_op_vec8; case 16: return nir_op_vec16; default: unreachable("bad component count"); @@ -1224,6 +1225,7 @@ nir_op_is_vec(nir_op op) case nir_op_vec2: case nir_op_vec3: case nir_op_vec4: + case nir_op_vec5: case nir_op_vec8: case nir_op_vec16: return true; diff --git a/src/compiler/nir/nir_builder.h b/src/compiler/nir/nir_builder.h index 6121bf3913b..a7e77f147ee 100644 --- a/src/compiler/nir/nir_builder.h +++ b/src/compiler/nir/nir_builder.h @@ -603,6 +603,7 @@ nir_fdot(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) case 2: return nir_fdot2(build, src0, src1); case 3: return nir_fdot3(build, src0, src1); case 4: return nir_fdot4(build, src0, src1); + case 5: return nir_fdot5(build, src0, src1); case 8: return nir_fdot8(build, src0, src1); case 16: return nir_fdot16(build, src0, src1); default: @@ -620,6 +621,7 @@ nir_ball_iequal(nir_builder *b, nir_ssa_def *src0, nir_ssa_def *src1) case 2: return nir_ball_iequal2(b, src0, src1); case 3: return nir_ball_iequal3(b, src0, src1); case 4: return nir_ball_iequal4(b, src0, src1); + case 5: return nir_ball_iequal5(b, src0, src1); case 8: return nir_ball_iequal8(b, src0, src1); case 16: return nir_ball_iequal16(b, src0, src1); default: @@ -641,6 +643,7 @@ nir_bany_inequal(nir_builder *b, nir_ssa_def *src0, nir_ssa_def *src1) case 2: return nir_bany_inequal2(b, src0, src1); case 3: return nir_bany_inequal3(b, src0, src1); case 4: return nir_bany_inequal4(b, src0, src1); + case 5: return nir_bany_inequal5(b, src0, src1); case 8: return nir_bany_inequal8(b, src0, src1); case 16: return nir_bany_inequal16(b, src0, src1); default: diff --git a/src/compiler/nir/nir_gather_ssa_types.c b/src/compiler/nir/nir_gather_ssa_types.c index d0d3e1cce52..c7c073c508c 100644 --- a/src/compiler/nir/nir_gather_ssa_types.c +++ b/src/compiler/nir/nir_gather_ssa_types.c @@ -112,6 +112,7 @@ nir_gather_ssa_types(nir_function_impl *impl, case nir_op_vec2: case nir_op_vec3: case nir_op_vec4: + case nir_op_vec5: case nir_op_vec8: case nir_op_vec16: for (unsigned i = 0; i < info->num_inputs; i++) { diff --git a/src/compiler/nir/nir_lower_alu_to_scalar.c b/src/compiler/nir/nir_lower_alu_to_scalar.c index 80d477a5933..f5884cef702 100644 --- a/src/compiler/nir/nir_lower_alu_to_scalar.c +++ b/src/compiler/nir/nir_lower_alu_to_scalar.c @@ -121,6 +121,7 @@ lower_alu_instr_scalar(nir_builder *b, nir_instr *instr, void *_data) switch (alu->op) { case nir_op_vec16: case nir_op_vec8: + case nir_op_vec5: case nir_op_vec4: case nir_op_vec3: case nir_op_vec2: diff --git a/src/compiler/nir/nir_lower_bool_to_bitsize.c b/src/compiler/nir/nir_lower_bool_to_bitsize.c index ac41a9cc644..7b71aceccc5 100644 --- a/src/compiler/nir/nir_lower_bool_to_bitsize.c +++ b/src/compiler/nir/nir_lower_bool_to_bitsize.c @@ -103,6 +103,7 @@ lower_alu_instr(nir_builder *b, nir_alu_instr *alu) case nir_op_vec2: case nir_op_vec3: case nir_op_vec4: + case nir_op_vec5: case nir_op_vec8: case nir_op_vec16: case nir_op_inot: @@ -152,6 +153,7 @@ lower_alu_instr(nir_builder *b, nir_alu_instr *alu) case nir_op_vec2: case nir_op_vec3: case nir_op_vec4: + case nir_op_vec5: case nir_op_vec8: case nir_op_vec16: case nir_op_inot: diff --git a/src/compiler/nir/nir_lower_bool_to_float.c b/src/compiler/nir/nir_lower_bool_to_float.c index 32f2ca056b2..ac6f581bbf1 100644 --- a/src/compiler/nir/nir_lower_bool_to_float.c +++ b/src/compiler/nir/nir_lower_bool_to_float.c @@ -56,6 +56,7 @@ lower_alu_instr(nir_builder *b, nir_alu_instr *alu) case nir_op_vec2: case nir_op_vec3: case nir_op_vec4: + case nir_op_vec5: case nir_op_vec8: case nir_op_vec16: if (alu->dest.dest.ssa.bit_size != 1) diff --git a/src/compiler/nir/nir_lower_bool_to_int32.c b/src/compiler/nir/nir_lower_bool_to_int32.c index 706f5d6ef8d..77e90fab6bc 100644 --- a/src/compiler/nir/nir_lower_bool_to_int32.c +++ b/src/compiler/nir/nir_lower_bool_to_int32.c @@ -53,6 +53,7 @@ lower_alu_instr(nir_alu_instr *alu) case nir_op_vec2: case nir_op_vec3: case nir_op_vec4: + case nir_op_vec5: case nir_op_vec8: case nir_op_vec16: case nir_op_inot: diff --git a/src/compiler/nir/nir_opcodes.py b/src/compiler/nir/nir_opcodes.py index 6a16e280d0c..f261ddff8f1 100644 --- a/src/compiler/nir/nir_opcodes.py +++ b/src/compiler/nir/nir_opcodes.py @@ -75,9 +75,9 @@ class Opcode(object): assert isinstance(algebraic_properties, str) assert isinstance(const_expr, str) assert len(input_sizes) == len(input_types) - assert 0 <= output_size <= 4 or (output_size == 8) or (output_size == 16) + assert 0 <= output_size <= 5 or (output_size == 8) or (output_size == 16) for size in input_sizes: - assert 0 <= size <= 4 or (size == 8) or (size == 16) + assert 0 <= size <= 5 or (size == 8) or (size == 16) if output_size != 0: assert size != 0 self.name = name @@ -575,6 +575,9 @@ def binop_reduce(name, output_size, output_type, src_type, prereduce_expr, opcode(name + "3" + suffix, output_size, output_type, [3, 3], [src_type, src_type], False, _2src_commutative, final(reduce_(reduce_(srcs[2], srcs[1]), srcs[0]))) + opcode(name + "5" + suffix, output_size, output_type, + [5, 5], [src_type, src_type], False, _2src_commutative, + final(reduce_(srcs[4], reduce_(reduce_(srcs[3], srcs[2]), reduce_(srcs[1], srcs[0]))))) def binop_reduce_all_sizes(name, output_size, src_type, prereduce_expr, reduce_expr, final_expr): @@ -1094,6 +1097,16 @@ dst.z = src2.x; dst.w = src3.x; """) +opcode("vec5", 5, tuint, + [1] * 5, [tuint] * 5, + False, "", """ +dst.x = src0.x; +dst.y = src1.x; +dst.z = src2.x; +dst.w = src3.x; +dst.e = src4.x; +""") + opcode("vec8", 8, tuint, [1] * 8, [tuint] * 8, False, "", """ diff --git a/src/compiler/nir/nir_opt_peephole_select.c b/src/compiler/nir/nir_opt_peephole_select.c index 7c40e4bac21..5d75b82f420 100644 --- a/src/compiler/nir/nir_opt_peephole_select.c +++ b/src/compiler/nir/nir_opt_peephole_select.c @@ -143,6 +143,7 @@ block_check_for_allowed_instrs(nir_block *block, unsigned *count, case nir_op_vec2: case nir_op_vec3: case nir_op_vec4: + case nir_op_vec5: case nir_op_vec8: case nir_op_vec16: movelike = true; diff --git a/src/compiler/nir/nir_print.c b/src/compiler/nir/nir_print.c index b3edd8ccf89..344ba7e969a 100644 --- a/src/compiler/nir/nir_print.c +++ b/src/compiler/nir/nir_print.c @@ -87,7 +87,7 @@ print_register(nir_register *reg, print_state *state) } static const char *sizes[] = { "error", "vec1", "vec2", "vec3", "vec4", - "error", "error", "error", "vec8", + "vec5", "error", "error", "vec8", "error", "error", "error", "error", "error", "error", "error", "vec16"};