From 953abc7d1e9d9807ce02e7ce1b6512173a0a738b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= Date: Fri, 23 Aug 2024 11:44:42 -0700 Subject: [PATCH] intel/perf: Add INTEL_PERF_FEATURE_METRIC_SYNC and check if KMD supports it MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Lionel Landwerlin Signed-off-by: José Roberto de Souza Part-of: --- src/intel/perf/intel_perf.h | 7 +++++++ src/intel/perf/xe/intel_perf.c | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/src/intel/perf/intel_perf.h b/src/intel/perf/intel_perf.h index 1f7be1b7026..4609bcf6111 100644 --- a/src/intel/perf/intel_perf.h +++ b/src/intel/perf/intel_perf.h @@ -322,6 +322,7 @@ enum intel_perf_features { INTEL_PERF_FEATURE_GLOBAL_SSEU = (1 << 1), /* Whether i915 has DRM_I915_QUERY_PERF_CONFIG support. */ INTEL_PERF_FEATURE_QUERY_PERF = (1 << 2), + INTEL_PERF_FEATURE_METRIC_SYNC = (1 << 3), }; struct intel_perf_config { @@ -574,6 +575,12 @@ intel_perf_has_global_sseu(const struct intel_perf_config *perf) return perf->features_supported & INTEL_PERF_FEATURE_GLOBAL_SSEU; } +static inline bool +intel_perf_has_metric_sync(const struct intel_perf_config *perf) +{ + return perf->features_supported & INTEL_PERF_FEATURE_METRIC_SYNC; +} + uint32_t intel_perf_get_n_passes(struct intel_perf_config *perf, const uint32_t *counter_indices, uint32_t counter_indices_count, diff --git a/src/intel/perf/xe/intel_perf.c b/src/intel/perf/xe/intel_perf.c index 1999437eb55..eac94d652e8 100644 --- a/src/intel/perf/xe/intel_perf.c +++ b/src/intel/perf/xe/intel_perf.c @@ -11,6 +11,7 @@ #include "perf/intel_perf.h" #include "intel_perf_common.h" #include "intel/common/intel_gem.h" +#include "intel/common/xe/intel_device_query.h" #include "intel/common/xe/intel_queue.h" #include "drm-uapi/xe_drm.h" @@ -47,6 +48,7 @@ uint64_t xe_perf_get_oa_format(struct intel_perf_config *perf) bool xe_oa_metrics_available(struct intel_perf_config *perf, int fd, bool use_register_snapshots) { + struct drm_xe_query_oa_units *oa_units; bool perf_oa_available = false; struct stat sb; @@ -72,6 +74,37 @@ xe_oa_metrics_available(struct intel_perf_config *perf, int fd, bool use_registe perf->features_supported |= INTEL_PERF_FEATURE_HOLD_PREEMPTION; + oa_units = xe_device_query_alloc_fetch(fd, DRM_XE_DEVICE_QUERY_OA_UNITS, NULL); + if (oa_units) { + uint8_t *poau; + uint32_t i; + + poau = (uint8_t *)oa_units->oa_units; + for (i = 0; i < oa_units->num_oa_units; i++) { + struct drm_xe_oa_unit *oa_unit = (struct drm_xe_oa_unit *)poau; + uint32_t engine_i; + bool render_found = false; + + for (engine_i = 0; engine_i < oa_unit->num_engines; engine_i++) { + if (oa_unit->eci[engine_i].engine_class == DRM_XE_ENGINE_CLASS_RENDER) { + render_found = true; + break; + } + } + + if (!render_found) + continue; + + if (oa_unit->capabilities & DRM_XE_OA_CAPS_SYNCS) { + perf->features_supported |= INTEL_PERF_FEATURE_METRIC_SYNC; + break; + } + poau += sizeof(*oa_unit) + oa_unit->num_engines * sizeof(oa_unit->eci[0]); + } + + free(oa_units); + } + return perf_oa_available; }