From 941e214fe7f7df2bf1e3f5b665aa7f48033198cf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Sat, 13 May 2023 17:49:41 -0400 Subject: [PATCH] radeonsi: reorder and comment tracked registers Acked-by: Qiang Yu Part-of: --- src/gallium/drivers/radeonsi/si_gfx_cs.c | 118 ++++++++++-------- src/gallium/drivers/radeonsi/si_state.h | 147 ++++++++++++----------- 2 files changed, 139 insertions(+), 126 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c index c19984b6658..a9a8de82a58 100644 --- a/src/gallium/drivers/radeonsi/si_gfx_cs.c +++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c @@ -233,66 +233,78 @@ void si_set_tracked_regs_to_clear_state(struct si_context *ctx) { STATIC_ASSERT(SI_NUM_TRACKED_CONTEXT_REGS <= sizeof(ctx->tracked_regs.context_reg_saved_mask) * 8); - ctx->tracked_regs.context_reg_value[SI_TRACKED_DB_RENDER_CONTROL] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_DB_COUNT_CONTROL] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_DB_RENDER_OVERRIDE2] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_DB_SHADER_CONTROL] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_CB_TARGET_MASK] = 0xffffffff; - ctx->tracked_regs.context_reg_value[SI_TRACKED_CB_DCC_CONTROL] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_SX_PS_DOWNCONVERT] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_SX_BLEND_OPT_EPSILON] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_SX_BLEND_OPT_CONTROL] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_SC_LINE_CNTL] = 0x00001000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_SC_AA_CONFIG] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_DB_EQAA] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_SC_MODE_CNTL_1] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_SU_PRIM_FILTER_CNTL] = 0; - ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_CL_VS_OUT_CNTL] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_CL_CLIP_CNTL] = 0x00090000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_SC_BINNER_CNTL_0] = 0x00000003; - ctx->tracked_regs.context_reg_value[SI_TRACKED_DB_PA_SC_VRS_OVERRIDE_CNTL] = 0x00000000; + ctx->tracked_regs.context_reg_value[SI_TRACKED_DB_RENDER_CONTROL] = 0; + ctx->tracked_regs.context_reg_value[SI_TRACKED_DB_COUNT_CONTROL] = 0; + + ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_SC_LINE_CNTL] = 0x1000; + ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_SC_AA_CONFIG] = 0; + + ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_SU_VTX_CNTL] = 0x5; ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_CL_GB_VERT_CLIP_ADJ] = 0x3f800000; ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_CL_GB_VERT_DISC_ADJ] = 0x3f800000; ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_CL_GB_HORZ_CLIP_ADJ] = 0x3f800000; ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_CL_GB_HORZ_DISC_ADJ] = 0x3f800000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_SU_HARDWARE_SCREEN_OFFSET] = 0; - ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_SU_VTX_CNTL] = 0x00000005; + + ctx->tracked_regs.context_reg_value[SI_TRACKED_SPI_SHADER_IDX_FORMAT] = 0; + ctx->tracked_regs.context_reg_value[SI_TRACKED_SPI_SHADER_POS_FORMAT] = 0; + + ctx->tracked_regs.context_reg_value[SI_TRACKED_SPI_SHADER_Z_FORMAT] = 0; + ctx->tracked_regs.context_reg_value[SI_TRACKED_SPI_SHADER_COL_FORMAT] = 0; + ctx->tracked_regs.context_reg_value[SI_TRACKED_SPI_BARYC_CNTL] = 0; + ctx->tracked_regs.context_reg_value[SI_TRACKED_SPI_PS_INPUT_ENA] = 0; + ctx->tracked_regs.context_reg_value[SI_TRACKED_SPI_PS_INPUT_ADDR] = 0; + + ctx->tracked_regs.context_reg_value[SI_TRACKED_DB_EQAA] = 0; + ctx->tracked_regs.context_reg_value[SI_TRACKED_DB_SHADER_CONTROL] = 0; + ctx->tracked_regs.context_reg_value[SI_TRACKED_CB_SHADER_MASK] = 0xffffffff; + ctx->tracked_regs.context_reg_value[SI_TRACKED_CB_TARGET_MASK] = 0xffffffff; + ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_CL_CLIP_CNTL] = 0x90000; + ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_CL_VS_OUT_CNTL] = 0; + ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_CL_VTE_CNTL] = 0; ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_SC_CLIPRECT_RULE] = 0xffff; ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_SC_LINE_STIPPLE] = 0; - ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_ESGS_RING_ITEMSIZE] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_1] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_2] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_3] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GSVS_RING_ITEMSIZE] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GS_MAX_VERT_OUT] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GS_VERT_ITEMSIZE] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GS_VERT_ITEMSIZE_1] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GS_VERT_ITEMSIZE_2] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GS_VERT_ITEMSIZE_3] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GS_INSTANCE_CNT] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GS_ONCHIP_CNTL] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GS_MODE] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_PRIMITIVEID_EN] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_REUSE_OFF] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_SPI_VS_OUT_CONFIG] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_GE_NGG_SUBGRP_CNTL] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_SPI_SHADER_IDX_FORMAT] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_SPI_SHADER_POS_FORMAT] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_CL_VTE_CNTL] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_CL_NGG_CNTL] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_SPI_PS_INPUT_ENA] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_SPI_PS_INPUT_ADDR] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_SPI_BARYC_CNTL] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_SPI_PS_IN_CONTROL] = 0x00000002; - ctx->tracked_regs.context_reg_value[SI_TRACKED_SPI_SHADER_Z_FORMAT] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_SPI_SHADER_COL_FORMAT] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_CB_SHADER_MASK] = 0xffffffff; - ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_TF_PARAM] = 0x00000000; - ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL] = 0x0000001e; /* From GFX8 */ + ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_SC_MODE_CNTL_1] = 0; + ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_SU_HARDWARE_SCREEN_OFFSET] = 0; + ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_SU_PRIM_FILTER_CNTL] = 0; + ctx->tracked_regs.context_reg_value[SI_TRACKED_SPI_PS_IN_CONTROL] = 0x2; + ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GS_INSTANCE_CNT] = 0; + ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GS_MAX_VERT_OUT] = 0; ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_SHADER_STAGES_EN] = 0; + ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_TF_PARAM] = 0; + ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL] = 0; + ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_SC_BINNER_CNTL_0] = 0x3; + ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_CL_NGG_CNTL] = 0; + ctx->tracked_regs.context_reg_value[SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP] = 0; + ctx->tracked_regs.context_reg_value[SI_TRACKED_GE_NGG_SUBGRP_CNTL] = 0; + ctx->tracked_regs.context_reg_value[SI_TRACKED_DB_PA_SC_VRS_OVERRIDE_CNTL] = 0; + + ctx->tracked_regs.context_reg_value[SI_TRACKED_SX_PS_DOWNCONVERT] = 0; + ctx->tracked_regs.context_reg_value[SI_TRACKED_SX_BLEND_OPT_EPSILON] = 0; + ctx->tracked_regs.context_reg_value[SI_TRACKED_SX_BLEND_OPT_CONTROL] = 0; + + ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_ESGS_RING_ITEMSIZE] = 0; + ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_REUSE_OFF] = 0; + + ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP] = 0; + ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GS_ONCHIP_CNTL] = 0; + + ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GSVS_RING_ITEMSIZE] = 0; + ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GS_MODE] = 0; + ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL] = 0x1e; + + ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_1] = 0; + ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_2] = 0; + ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_3] = 0; + + ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GS_VERT_ITEMSIZE] = 0; + ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GS_VERT_ITEMSIZE_1] = 0; + ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GS_VERT_ITEMSIZE_2] = 0; + ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GS_VERT_ITEMSIZE_3] = 0; + + ctx->tracked_regs.context_reg_value[SI_TRACKED_DB_RENDER_OVERRIDE2] = 0; + ctx->tracked_regs.context_reg_value[SI_TRACKED_SPI_VS_OUT_CONFIG] = 0; + ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_PRIMITIVEID_EN] = 0; + ctx->tracked_regs.context_reg_value[SI_TRACKED_CB_DCC_CONTROL] = 0; /* Set all cleared context registers to saved. */ ctx->tracked_regs.context_reg_saved_mask = BITFIELD64_MASK(SI_NUM_TRACKED_CONTEXT_REGS); diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h index f90fbe9f150..783cf90dbaa 100644 --- a/src/gallium/drivers/radeonsi/si_state.h +++ b/src/gallium/drivers/radeonsi/si_state.h @@ -229,101 +229,102 @@ struct si_shader_data { uint32_t sh_base[SI_NUM_SHADERS]; }; -/* The list of registers whose emitted values are remembered by si_context. */ +/* Context registers whose values are tracked by si_context. */ enum si_tracked_context_reg { - SI_TRACKED_DB_RENDER_CONTROL, /* 2 consecutive registers */ + /* 2 consecutive registers */ + SI_TRACKED_DB_RENDER_CONTROL, SI_TRACKED_DB_COUNT_CONTROL, - SI_TRACKED_DB_RENDER_OVERRIDE2, - SI_TRACKED_DB_SHADER_CONTROL, - - SI_TRACKED_CB_TARGET_MASK, - SI_TRACKED_CB_DCC_CONTROL, - - SI_TRACKED_SX_PS_DOWNCONVERT, /* 3 consecutive registers */ - SI_TRACKED_SX_BLEND_OPT_EPSILON, - SI_TRACKED_SX_BLEND_OPT_CONTROL, - - SI_TRACKED_PA_SC_LINE_CNTL, /* 2 consecutive registers */ + /* 2 consecutive registers */ + SI_TRACKED_PA_SC_LINE_CNTL, SI_TRACKED_PA_SC_AA_CONFIG, - SI_TRACKED_DB_EQAA, - SI_TRACKED_PA_SC_MODE_CNTL_1, - - SI_TRACKED_PA_SU_PRIM_FILTER_CNTL, - SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL, - - SI_TRACKED_PA_CL_VS_OUT_CNTL, - SI_TRACKED_PA_CL_CLIP_CNTL, - - SI_TRACKED_PA_SC_BINNER_CNTL_0, - - SI_TRACKED_DB_PA_SC_VRS_OVERRIDE_CNTL, - - SI_TRACKED_PA_SU_VTX_CNTL, /* 5 consecutive registers */ + /* 5 consecutive registers */ + SI_TRACKED_PA_SU_VTX_CNTL, SI_TRACKED_PA_CL_GB_VERT_CLIP_ADJ, SI_TRACKED_PA_CL_GB_VERT_DISC_ADJ, SI_TRACKED_PA_CL_GB_HORZ_CLIP_ADJ, SI_TRACKED_PA_CL_GB_HORZ_DISC_ADJ, - SI_TRACKED_PA_SU_HARDWARE_SCREEN_OFFSET, - - SI_TRACKED_PA_SC_CLIPRECT_RULE, - - SI_TRACKED_PA_SC_LINE_STIPPLE, - - SI_TRACKED_VGT_ESGS_RING_ITEMSIZE, - - SI_TRACKED_VGT_GSVS_RING_OFFSET_1, /* 3 consecutive registers */ - SI_TRACKED_VGT_GSVS_RING_OFFSET_2, - SI_TRACKED_VGT_GSVS_RING_OFFSET_3, - - SI_TRACKED_VGT_GSVS_RING_ITEMSIZE, - SI_TRACKED_VGT_GS_MAX_VERT_OUT, - - SI_TRACKED_VGT_GS_VERT_ITEMSIZE, /* 4 consecutive registers */ - SI_TRACKED_VGT_GS_VERT_ITEMSIZE_1, - SI_TRACKED_VGT_GS_VERT_ITEMSIZE_2, - SI_TRACKED_VGT_GS_VERT_ITEMSIZE_3, - - SI_TRACKED_VGT_GS_INSTANCE_CNT, - SI_TRACKED_VGT_GS_ONCHIP_CNTL, - SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP, - SI_TRACKED_VGT_GS_MODE, - SI_TRACKED_VGT_PRIMITIVEID_EN, - SI_TRACKED_VGT_REUSE_OFF, - SI_TRACKED_SPI_VS_OUT_CONFIG, - SI_TRACKED_PA_CL_VTE_CNTL, - SI_TRACKED_PA_CL_NGG_CNTL, - SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP, - SI_TRACKED_GE_NGG_SUBGRP_CNTL, - - SI_TRACKED_SPI_SHADER_IDX_FORMAT, /* 2 consecutive registers */ + /* 2 consecutive registers */ + SI_TRACKED_SPI_SHADER_IDX_FORMAT, SI_TRACKED_SPI_SHADER_POS_FORMAT, - SI_TRACKED_SPI_PS_INPUT_ENA, /* 2 consecutive registers */ - SI_TRACKED_SPI_PS_INPUT_ADDR, - - SI_TRACKED_SPI_BARYC_CNTL, - SI_TRACKED_SPI_PS_IN_CONTROL, - - SI_TRACKED_SPI_SHADER_Z_FORMAT, /* 2 consecutive registers */ + /* 2 consecutive registers */ + SI_TRACKED_SPI_SHADER_Z_FORMAT, SI_TRACKED_SPI_SHADER_COL_FORMAT, + SI_TRACKED_SPI_BARYC_CNTL, + + /* 2 consecutive registers */ + SI_TRACKED_SPI_PS_INPUT_ENA, + SI_TRACKED_SPI_PS_INPUT_ADDR, + + SI_TRACKED_DB_EQAA, + SI_TRACKED_DB_SHADER_CONTROL, SI_TRACKED_CB_SHADER_MASK, - SI_TRACKED_VGT_TF_PARAM, - SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL, + SI_TRACKED_CB_TARGET_MASK, + SI_TRACKED_PA_CL_CLIP_CNTL, + SI_TRACKED_PA_CL_VS_OUT_CNTL, + SI_TRACKED_PA_CL_VTE_CNTL, + SI_TRACKED_PA_SC_CLIPRECT_RULE, + SI_TRACKED_PA_SC_LINE_STIPPLE, + SI_TRACKED_PA_SC_MODE_CNTL_1, + SI_TRACKED_PA_SU_HARDWARE_SCREEN_OFFSET, + SI_TRACKED_PA_SU_PRIM_FILTER_CNTL, + SI_TRACKED_SPI_PS_IN_CONTROL, + SI_TRACKED_VGT_GS_INSTANCE_CNT, + SI_TRACKED_VGT_GS_MAX_VERT_OUT, SI_TRACKED_VGT_SHADER_STAGES_EN, + SI_TRACKED_VGT_TF_PARAM, + SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL, /* GFX8+ */ + SI_TRACKED_PA_SC_BINNER_CNTL_0, /* GFX9+ */ + SI_TRACKED_PA_CL_NGG_CNTL, /* GFX10+ */ + SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP, /* GFX10+ */ + SI_TRACKED_GE_NGG_SUBGRP_CNTL, /* GFX10+ */ + SI_TRACKED_DB_PA_SC_VRS_OVERRIDE_CNTL, /* GFX10.3+ */ + + /* 3 consecutive registers */ + SI_TRACKED_SX_PS_DOWNCONVERT, /* GFX8+ */ + SI_TRACKED_SX_BLEND_OPT_EPSILON, /* GFX8+ */ + SI_TRACKED_SX_BLEND_OPT_CONTROL, /* GFX8+ */ + + /* The slots below can be reused by other generations. */ + SI_TRACKED_VGT_ESGS_RING_ITEMSIZE, /* GFX6-8 (GFX9+ can reuse this slot) */ + SI_TRACKED_VGT_REUSE_OFF, /* GFX6-8 (GFX9+ can reuse this slot) */ + + SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP, /* GFX9-10 - the slots above can be reused */ + SI_TRACKED_VGT_GS_ONCHIP_CNTL, /* GFX9-10 - the slots above can be reused */ + + SI_TRACKED_VGT_GSVS_RING_ITEMSIZE, /* GFX6-10 (GFX11+ can reuse this slot) */ + SI_TRACKED_VGT_GS_MODE, /* GFX6-10 (GFX11+ can reuse this slot) */ + SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL, /* GFX6-10 (GFX11+ can reuse this slot) */ + + /* 3 consecutive registers */ + SI_TRACKED_VGT_GSVS_RING_OFFSET_1, /* GFX6-10 (GFX11+ can reuse this slot) */ + SI_TRACKED_VGT_GSVS_RING_OFFSET_2, /* GFX6-10 (GFX11+ can reuse this slot) */ + SI_TRACKED_VGT_GSVS_RING_OFFSET_3, /* GFX6-10 (GFX11+ can reuse this slot) */ + + /* 4 consecutive registers */ + SI_TRACKED_VGT_GS_VERT_ITEMSIZE, /* GFX6-10 (GFX11+ can reuse this slot) */ + SI_TRACKED_VGT_GS_VERT_ITEMSIZE_1, /* GFX6-10 (GFX11+ can reuse this slot) */ + SI_TRACKED_VGT_GS_VERT_ITEMSIZE_2, /* GFX6-10 (GFX11+ can reuse this slot) */ + SI_TRACKED_VGT_GS_VERT_ITEMSIZE_3, /* GFX6-10 (GFX11+ can reuse this slot) */ + + SI_TRACKED_DB_RENDER_OVERRIDE2, /* GFX6-xx (TBD) */ + SI_TRACKED_SPI_VS_OUT_CONFIG, /* GFX6-xx (TBD) */ + SI_TRACKED_VGT_PRIMITIVEID_EN, /* GFX6-xx (TBD) */ + SI_TRACKED_CB_DCC_CONTROL, /* GFX8-xx (TBD) */ SI_NUM_TRACKED_CONTEXT_REGS, }; +/* Non-context registers whose values are tracked by si_context. */ enum si_tracked_other_reg { - /* Non-context registers: */ - SI_TRACKED_GE_PC_ALLOC, - SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS, - SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS, + SI_TRACKED_GE_PC_ALLOC, /* GFX10+ */ + SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS, /* GFX7+ */ + SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS, /* GFX10+ */ SI_NUM_TRACKED_OTHER_REGS, };