From 93f24f0bd02916d9ce4cc452312c19e9cca5d299 Mon Sep 17 00:00:00 2001 From: Karol Herbst Date: Wed, 11 Jun 2025 02:08:26 +0200 Subject: [PATCH] rusticl: support cl_khr_extended_bit_ops Reviewed-by: Alyssa Rosenzweig Part-of: --- docs/features.txt | 2 +- docs/relnotes/new_features.txt | 1 + src/gallium/frontends/rusticl/core/device.rs | 4 ++++ 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/docs/features.txt b/docs/features.txt index a588d8272aa..941b0331c9c 100644 --- a/docs/features.txt +++ b/docs/features.txt @@ -822,7 +822,7 @@ Rusticl extensions that are not part of any OpenCL version: cl_khr_egl_image not started cl_khr_expect_assume in progress (hints are ignored) cl_khr_extended_async_copies not started - cl_khr_extended_bit_ops in progress + cl_khr_extended_bit_ops DONE cl_khr_fp16 DONE (asahi, freedreno, llvmpipe, panfrost, radeonsi, zink) cl_khr_gl_depth_images not started cl_khr_gl_msaa_sharing not started diff --git a/docs/relnotes/new_features.txt b/docs/relnotes/new_features.txt index c99099dbd96..e565681c26f 100644 --- a/docs/relnotes/new_features.txt +++ b/docs/relnotes/new_features.txt @@ -52,3 +52,4 @@ VK_EXT_descriptor_indexing on panvk/v10+ cl_khr_priority_hints VK_KHR_maintenance6 on panvk/v10+ CL_sRGBA and CL_sBGRA images +cl_khr_extended_bit_ops diff --git a/src/gallium/frontends/rusticl/core/device.rs b/src/gallium/frontends/rusticl/core/device.rs index 73c1b80cbad..a9aaa79621e 100644 --- a/src/gallium/frontends/rusticl/core/device.rs +++ b/src/gallium/frontends/rusticl/core/device.rs @@ -601,6 +601,7 @@ impl DeviceBase { add_ext(1, 0, 0, "cl_khr_byte_addressable_store"); add_ext(1, 0, 0, "cl_khr_create_command_queue"); add_ext(1, 0, 0, "cl_khr_expect_assume"); + add_ext(1, 0, 0, "cl_khr_extended_bit_ops"); add_ext(1, 0, 0, "cl_khr_extended_versioning"); add_ext(1, 0, 0, "cl_khr_global_int32_base_atomics"); add_ext(1, 0, 0, "cl_khr_global_int32_extended_atomics"); @@ -620,12 +621,14 @@ impl DeviceBase { "__opencl_c_integer_dot_product_input_4x8bit_packed", ); + add_spirv(c"SPV_KHR_bit_instructions"); add_spirv(c"SPV_KHR_expect_assume"); add_spirv(c"SPV_KHR_float_controls"); add_spirv(c"SPV_KHR_integer_dot_product"); add_spirv(c"SPV_KHR_no_integer_wrap_decoration"); add_cap(SpvCapability::SpvCapabilityAddresses); + add_cap(SpvCapability::SpvCapabilityBitInstructions); add_cap(SpvCapability::SpvCapabilityDotProduct); add_cap(SpvCapability::SpvCapabilityDotProductInput4x8Bit); add_cap(SpvCapability::SpvCapabilityDotProductInput4x8BitPacked); @@ -1213,6 +1216,7 @@ impl DeviceBase { pub fn cl_features(&self) -> clc_optional_features { let subgroups_supported = self.subgroups_supported(); clc_optional_features { + extended_bit_ops: true, fp16: self.fp16_supported(), fp64: self.fp64_supported(), int64: self.int64_supported(),