From 93a327c4e6eab5c9a64ccd793f50c432347dc75d Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Thu, 23 Jan 2025 14:57:26 +0200 Subject: [PATCH] anv/brw: move INTEL_MSAA_* flag computation to the compiler Signed-off-by: Lionel Landwerlin Reviewed-by: Caio Oliveira Part-of: --- src/intel/compiler/intel_shader_enums.h | 41 +++++++++++++++++++++++++ src/intel/vulkan/genX_gfx_state.c | 34 ++++++-------------- 2 files changed, 50 insertions(+), 25 deletions(-) diff --git a/src/intel/compiler/intel_shader_enums.h b/src/intel/compiler/intel_shader_enums.h index 73008587ec9..15a03ba781d 100644 --- a/src/intel/compiler/intel_shader_enums.h +++ b/src/intel/compiler/intel_shader_enums.h @@ -341,6 +341,47 @@ intel_fs_is_coarse(enum intel_sometimes shader_coarse_pixel_dispatch, return (pushed_msaa_flags & INTEL_MSAA_FLAG_COARSE_RT_WRITES) != 0; } +struct intel_fs_params { + bool shader_sample_shading; + float shader_min_sample_shading; + bool state_sample_shading; + uint32_t rasterization_samples; + bool coarse_pixel; + bool alpha_to_coverage; +}; + +static inline enum intel_msaa_flags +intel_fs_msaa_flags(struct intel_fs_params params) +{ + enum intel_msaa_flags fs_msaa_flags = INTEL_MSAA_FLAG_ENABLE_DYNAMIC; + + if (params.rasterization_samples > 1) { + fs_msaa_flags |= INTEL_MSAA_FLAG_MULTISAMPLE_FBO; + + if (params.shader_sample_shading) + fs_msaa_flags |= INTEL_MSAA_FLAG_PERSAMPLE_DISPATCH; + + if (params.shader_sample_shading || + (params.state_sample_shading && + (params.shader_min_sample_shading * + params.rasterization_samples) > 1)) { + fs_msaa_flags |= INTEL_MSAA_FLAG_PERSAMPLE_DISPATCH | + INTEL_MSAA_FLAG_PERSAMPLE_INTERP; + } + } + + if (!(fs_msaa_flags & INTEL_MSAA_FLAG_PERSAMPLE_DISPATCH) && + params.coarse_pixel) { + fs_msaa_flags |= INTEL_MSAA_FLAG_COARSE_PI_MSG | + INTEL_MSAA_FLAG_COARSE_RT_WRITES; + } + + if (params.alpha_to_coverage) + fs_msaa_flags |= INTEL_MSAA_FLAG_ALPHA_TO_COVERAGE; + + return fs_msaa_flags; +} + #ifdef __cplusplus } /* extern "C" */ #endif diff --git a/src/intel/vulkan/genX_gfx_state.c b/src/intel/vulkan/genX_gfx_state.c index c65d094ce5f..a00424925af 100644 --- a/src/intel/vulkan/genX_gfx_state.c +++ b/src/intel/vulkan/genX_gfx_state.c @@ -712,31 +712,15 @@ update_fs_msaa_flags(struct anv_gfx_dynamic_state *hw_state, wm_prog_data->alpha_to_coverage != INTEL_SOMETIMES) return; - enum intel_msaa_flags fs_msaa_flags = INTEL_MSAA_FLAG_ENABLE_DYNAMIC; - - if (dyn->ms.rasterization_samples > 1) { - fs_msaa_flags |= INTEL_MSAA_FLAG_MULTISAMPLE_FBO; - - if (wm_prog_data->sample_shading) { - assert(wm_prog_data->persample_dispatch != INTEL_NEVER); - fs_msaa_flags |= INTEL_MSAA_FLAG_PERSAMPLE_DISPATCH; - } - if ((pipeline->sample_shading_enable && - (pipeline->min_sample_shading * dyn->ms.rasterization_samples) > 1) || - wm_prog_data->sample_shading) { - fs_msaa_flags |= INTEL_MSAA_FLAG_PERSAMPLE_DISPATCH | - INTEL_MSAA_FLAG_PERSAMPLE_INTERP; - } - } - - if (wm_prog_data->coarse_pixel_dispatch == INTEL_SOMETIMES && - !(fs_msaa_flags & INTEL_MSAA_FLAG_PERSAMPLE_DISPATCH)) { - fs_msaa_flags |= INTEL_MSAA_FLAG_COARSE_PI_MSG | - INTEL_MSAA_FLAG_COARSE_RT_WRITES; - } - - if (dyn->ms.alpha_to_coverage_enable) - fs_msaa_flags |= INTEL_MSAA_FLAG_ALPHA_TO_COVERAGE; + enum intel_msaa_flags fs_msaa_flags = + intel_fs_msaa_flags((struct intel_fs_params) { + .shader_sample_shading = wm_prog_data->sample_shading, + .shader_min_sample_shading = pipeline->min_sample_shading, + .state_sample_shading = pipeline->sample_shading_enable, + .rasterization_samples = dyn->ms.rasterization_samples, + .coarse_pixel = !vk_fragment_shading_rate_is_disabled(&dyn->fsr), + .alpha_to_coverage = dyn->ms.alpha_to_coverage_enable, + }); SET(FS_MSAA_FLAGS, fs_msaa_flags, fs_msaa_flags); }