From 93706d5c2fb8cd47fa444fd8598b5cb190cf74a7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Tapani=20P=C3=A4lli?= <tapani.palli@intel.com>
Date: Thu, 18 Jan 2024 07:20:24 +0200
Subject: [PATCH] iris: expand pre-hiz data cache flush to gfx >= 125
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Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27132>
---
 src/gallium/drivers/iris/iris_resolve.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/iris/iris_resolve.c b/src/gallium/drivers/iris/iris_resolve.c
index d245fb55bf1..a6c2c62d785 100644
--- a/src/gallium/drivers/iris/iris_resolve.c
+++ b/src/gallium/drivers/iris/iris_resolve.c
@@ -703,7 +703,7 @@ iris_hiz_exec(struct iris_context *ice,
    /* A data cache flush is not suggested by HW docs, but we found it to fix
     * a number of failures.
     */
-   unsigned wa_flush = intel_device_info_is_dg2(batch->screen->devinfo) &&
+   unsigned wa_flush = devinfo->verx10 >= 125 &&
                        res->aux.usage == ISL_AUX_USAGE_HIZ_CCS ?
                        PIPE_CONTROL_DATA_CACHE_FLUSH : 0;