From 92464109e3783a7552cd9203cc2cdd701c548653 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 13 Dec 2024 06:28:15 +0100 Subject: [PATCH] ac/nir: Mark when pre-rast output is used as varying or sysval. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In this commit, just collect the info. It will be taken into use by subsequent commits. Signed-off-by: Timur Kristóf Acked-by: Marek Olšák Reviewed-by: Samuel Pitoiset Part-of: --- src/amd/common/ac_nir.c | 6 ++++++ src/amd/common/ac_nir_helpers.h | 4 ++++ src/amd/common/ac_nir_lower_ngg.c | 17 +++++++++++++---- 3 files changed, 23 insertions(+), 4 deletions(-) diff --git a/src/amd/common/ac_nir.c b/src/amd/common/ac_nir.c index 83ab26eba20..ca9a37fa1f0 100644 --- a/src/amd/common/ac_nir.c +++ b/src/amd/common/ac_nir.c @@ -287,6 +287,11 @@ void ac_nir_gather_prerast_store_output_info(nir_builder *b, nir_intrinsic_instr info->stream |= stream << (c * 2); info->components_mask |= BITFIELD_BIT(c); + if (!io_sem.no_varying) + info->as_varying_mask |= BITFIELD_BIT(c); + if (!io_sem.no_sysval_output) + info->as_sysval_mask |= BITFIELD_BIT(c); + nir_def *store_component = nir_channel(b, intrin->src[0].ssa, i); if (non_dedicated_16bit) { @@ -1026,6 +1031,7 @@ ac_nir_lower_legacy_vs(nir_shader *nir, * or MS). */ out.outputs[VARYING_SLOT_PRIMITIVE_ID][0] = nir_load_primitive_id(&b); + out.infos[VARYING_SLOT_PRIMITIVE_ID].as_varying_mask = 0x1; /* Update outputs_written to reflect that the pass added a new output. */ nir->info.outputs_written |= BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_ID); diff --git a/src/amd/common/ac_nir_helpers.h b/src/amd/common/ac_nir_helpers.h index fe14065f997..53ca009beca 100644 --- a/src/amd/common/ac_nir_helpers.h +++ b/src/amd/common/ac_nir_helpers.h @@ -52,6 +52,10 @@ typedef struct uint8_t stream; /* Bitmask of components used: 4 bits per slot, 1 bit per component. */ uint8_t components_mask : 4; + /* Bitmask of components that are used as varying, 1 bit per component. */ + uint8_t as_varying_mask : 4; + /* Bitmask of components that are used as sysval, 1 bit per component. */ + uint8_t as_sysval_mask : 4; } ac_nir_prerast_per_output_info; typedef struct diff --git a/src/amd/common/ac_nir_lower_ngg.c b/src/amd/common/ac_nir_lower_ngg.c index 03f55a1c550..f12bf97b414 100644 --- a/src/amd/common/ac_nir_lower_ngg.c +++ b/src/amd/common/ac_nir_lower_ngg.c @@ -636,7 +636,7 @@ emit_ngg_nogs_prim_export(nir_builder *b, lower_ngg_nogs_state *s, nir_def *arg) nir_def *prim_id = nir_load_primitive_id(b); nir_def *undef = nir_undef(b, 1, 32); ac_nir_prerast_out out = { - .infos = {{.components_mask = 1}}, + .infos = {{.components_mask = 1, .as_varying_mask = 1}}, .outputs = {{prim_id, undef, undef, undef}} }; @@ -690,7 +690,7 @@ emit_ngg_nogs_prim_id_store_per_prim_to_attr_ring(nir_builder *b, lower_ngg_nogs const uint8_t offset = s->options->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID]; ac_nir_prerast_out out = { - .infos = {{.components_mask = 1}}, + .infos = {{.components_mask = 1, .as_varying_mask = 1}}, .outputs = {{nir_load_primitive_id(b), NULL, NULL, NULL}} }; @@ -716,6 +716,7 @@ emit_store_ngg_nogs_es_primitive_id(nir_builder *b, lower_ngg_nogs_state *s) } s->out.outputs[VARYING_SLOT_PRIMITIVE_ID][0] = prim_id; + s->out.infos[VARYING_SLOT_PRIMITIVE_ID].as_varying_mask |= 1; /* Update outputs_written to reflect that the pass added a new output. */ b->shader->info.outputs_written |= VARYING_BIT_PRIMITIVE_ID; @@ -2517,7 +2518,7 @@ export_pos0_wait_attr_ring(nir_builder *b, nir_if *if_es_thread, nir_def *output /* Create phi for the position output values. */ ac_nir_prerast_out out = { .outputs = {{outputs[VARYING_SLOT_POS][0], outputs[VARYING_SLOT_POS][1], outputs[VARYING_SLOT_POS][2], outputs[VARYING_SLOT_POS][3]}}, - .infos = {{.components_mask = 0xf}}, + .infos = {{.components_mask = 0xf, .as_sysval_mask = 0xf}}, }; b->cursor = nir_after_cf_list(&b->impl->body); @@ -3844,6 +3845,11 @@ update_ms_output_info(const nir_io_semantics io_sem, for (unsigned base_off = base_off_start; base_off < num_slots; ++base_off) { ac_nir_prerast_per_output_info *info = &s->out.infos[io_sem.location + base_off]; info->components_mask |= components_mask; + + if (!io_sem.no_sysval_output) + info->as_sysval_mask |= components_mask; + if (!io_sem.no_varying) + info->as_varying_mask |= components_mask; } } @@ -4521,8 +4527,11 @@ emit_ms_primitive(nir_builder *b, nir_def *index, nir_def *row, bool exports, bo ms_emit_arrayed_outputs(b, index, per_primitive_outputs, s); /* Insert layer output store if the pipeline uses multiview but the API shader doesn't write it. */ - if (s->insert_layer_output) + if (s->insert_layer_output) { s->out.outputs[VARYING_SLOT_LAYER][0] = nir_load_view_index(b); + s->out.infos[VARYING_SLOT_LAYER].as_sysval_mask |= 1; + s->out.infos[VARYING_SLOT_LAYER].as_varying_mask |= 1; + } if (exports) { const uint64_t outputs_mask = per_primitive_outputs & MS_PRIM_ARG_EXP_MASK;