From 91e533c6aa04026bb1613adf48e284d1d2c92107 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
Date: Sun, 5 Jun 2022 21:46:14 -0400
Subject: [PATCH] radeonsi: report correct maximum compute grid sizes

Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16901>
---
 src/gallium/drivers/radeonsi/si_get.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c
index bf0462a1f5b..7ac187ed2ff 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -817,9 +817,9 @@ static int si_get_compute_param(struct pipe_screen *screen, enum pipe_shader_ir
    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
       if (ret) {
          uint64_t *grid_size = ret;
-         grid_size[0] = 65535;
-         grid_size[1] = 65535;
-         grid_size[2] = 65535;
+         grid_size[0] = UINT32_MAX;
+         grid_size[1] = UINT32_MAX;
+         grid_size[2] = UINT32_MAX;
       }
       return 3 * sizeof(uint64_t);