From 91c91bb972bcb219b4a3c01a14262982284fda23 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Thu, 27 Apr 2023 19:33:32 +0800 Subject: [PATCH] radeonsi: lower non uniform texture access when aco MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit aco need all resource have been lowered to descriptor. Reviewed-by: Marek Olšák Signed-off-by: Qiang Yu Part-of: --- src/gallium/drivers/radeonsi/si_shader.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index 122b63fbe8a..29602d240e8 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -2138,6 +2138,14 @@ struct nir_shader *si_get_nir_shader(struct si_shader *shader, if (!sel->screen->info.has_image_opcodes) NIR_PASS(progress, nir, ac_nir_lower_image_opcodes); + /* LLVM does not work well with this, so is handled in llvm backend waterfall. */ + if (shader->use_aco && sel->info.has_non_uniform_tex_access) { + nir_lower_non_uniform_access_options options = { + .types = nir_lower_non_uniform_texture_access, + }; + NIR_PASS(progress, nir, nir_lower_non_uniform_access, &options); + } + NIR_PASS(progress, nir, si_nir_lower_resource, shader, args); bool is_last_vgt_stage =