diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp
index d52e703d7df..55d44c64c9e 100644
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -11506,9 +11506,9 @@ create_fs_exports(isel_context* ctx)
 
          out.slot = compacted_mrt_index;
          out.write_mask = ctx->outputs.mask[i];
-         out.col_format = (ctx->options->key.ps.col_format >> (4 * idx)) & 0xf;
-         out.is_int8 = (ctx->options->key.ps.is_int8 >> idx) & 1;
-         out.is_int10 = (ctx->options->key.ps.is_int10 >> idx) & 1;
+         out.col_format = (ctx->options->key.ps.spi_shader_col_format >> (4 * idx)) & 0xf;
+         out.is_int8 = (ctx->options->key.ps.color_is_int8 >> idx) & 1;
+         out.is_int10 = (ctx->options->key.ps.color_is_int10 >> idx) & 1;
          out.enable_mrt_output_nan_fixup = (ctx->options->key.ps.enable_mrt_output_nan_fixup >> idx) & 1;
 
          for (unsigned c = 0; c < 4; ++c) {
diff --git a/src/amd/compiler/aco_shader_info.h b/src/amd/compiler/aco_shader_info.h
index a164664a844..e5ce4c8569d 100644
--- a/src/amd/compiler/aco_shader_info.h
+++ b/src/amd/compiler/aco_shader_info.h
@@ -156,9 +156,9 @@ struct aco_stage_input {
    } tcs;
 
    struct {
-      uint32_t col_format;
-      uint32_t is_int8;
-      uint32_t is_int10;
+      uint32_t spi_shader_col_format;
+      uint32_t color_is_int8;
+      uint32_t color_is_int10;
       uint8_t enable_mrt_output_nan_fixup;
 
       /* Used to export alpha through MRTZ for alpha-to-coverage (GFX11+). */
diff --git a/src/amd/vulkan/radv_aco_shader_info.h b/src/amd/vulkan/radv_aco_shader_info.h
index cb2f72f8ffa..cb70f7233e5 100644
--- a/src/amd/vulkan/radv_aco_shader_info.h
+++ b/src/amd/vulkan/radv_aco_shader_info.h
@@ -134,9 +134,9 @@ radv_aco_convert_pipe_key(struct aco_stage_input *aco_info,
    ASSIGN_FIELD_CP(vs.vertex_attribute_strides);
    ASSIGN_FIELD_CP(vs.vertex_binding_align);
    ASSIGN_FIELD(tcs.tess_input_vertices);
-   ASSIGN_FIELD(ps.col_format);
-   ASSIGN_FIELD(ps.is_int8);
-   ASSIGN_FIELD(ps.is_int10);
+   ASSIGN_FIELD(ps.spi_shader_col_format);
+   ASSIGN_FIELD(ps.color_is_int8);
+   ASSIGN_FIELD(ps.color_is_int10);
    ASSIGN_FIELD(ps.enable_mrt_output_nan_fixup);
    ASSIGN_FIELD(ps.alpha_to_coverage_via_mrtz);
    ASSIGN_FIELD(ps.mrt0_is_dual_src);
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c
index c6fd844c244..03638630cf8 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -567,9 +567,9 @@ si_llvm_init_export_args(struct radv_shader_context *ctx, LLVMValueRef *values,
 
    bool is_16bit = ac_get_type_size(LLVMTypeOf(values[0])) == 2;
    if (ctx->stage == MESA_SHADER_FRAGMENT) {
-      unsigned col_format = (ctx->options->key.ps.col_format >> (4 * index)) & 0xf;
-      bool is_int8 = (ctx->options->key.ps.is_int8 >> index) & 1;
-      bool is_int10 = (ctx->options->key.ps.is_int10 >> index) & 1;
+      unsigned col_format = (ctx->options->key.ps.spi_shader_col_format >> (4 * index)) & 0xf;
+      bool is_int8 = (ctx->options->key.ps.color_is_int8 >> index) & 1;
+      bool is_int10 = (ctx->options->key.ps.color_is_int10 >> index) & 1;
       bool enable_mrt_output_nan_fixup = (ctx->options->key.ps.enable_mrt_output_nan_fixup >> index) & 1;
 
       LLVMValueRef (*packf)(struct ac_llvm_context * ctx, LLVMValueRef args[2]) = NULL;
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index a250fa2eb1e..212370616ee 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2215,7 +2215,7 @@ radv_remove_color_exports(const struct radv_pipeline_key *pipeline_key, nir_shad
       if (idx < 0)
          continue;
 
-      unsigned col_format = (pipeline_key->ps.col_format >> (4 * idx)) & 0xf;
+      unsigned col_format = (pipeline_key->ps.spi_shader_col_format >> (4 * idx)) & 0xf;
       unsigned cb_target_mask = (pipeline_key->ps.cb_target_mask >> (4 * idx)) & 0xf;
 
       if (col_format == V_028714_SPI_SHADER_ZERO ||
@@ -2750,12 +2750,12 @@ radv_generate_graphics_pipeline_key(const struct radv_graphics_pipeline *pipelin
       }
    }
 
-   key.ps.col_format = blend->spi_shader_col_format;
+   key.ps.spi_shader_col_format = blend->spi_shader_col_format;
    key.ps.cb_target_mask = blend->cb_target_mask;
    key.ps.mrt0_is_dual_src = blend->mrt0_is_dual_src;
    if (device->physical_device->rad_info.gfx_level < GFX8) {
-      key.ps.is_int8 = blend->col_format_is_int8;
-      key.ps.is_int10 = blend->col_format_is_int10;
+      key.ps.color_is_int8 = blend->col_format_is_int8;
+      key.ps.color_is_int10 = blend->col_format_is_int10;
    }
    if (device->physical_device->rad_info.gfx_level >= GFX11 && state->ms) {
       key.ps.alpha_to_coverage_via_mrtz = state->ms->alpha_to_coverage_enable;
@@ -3753,9 +3753,9 @@ radv_pipeline_create_ps_epilog(struct radv_graphics_pipeline *pipeline,
    if (pipeline->base.shaders[MESA_SHADER_FRAGMENT] &&
        pipeline->base.shaders[MESA_SHADER_FRAGMENT]->info.ps.has_epilog && !pipeline->ps_epilog) {
       struct radv_ps_epilog_key epilog_key = {
-         .spi_shader_col_format = pipeline_key->ps.col_format,
-         .color_is_int8 = pipeline_key->ps.is_int8,
-         .color_is_int10 = pipeline_key->ps.is_int10,
+         .spi_shader_col_format = pipeline_key->ps.spi_shader_col_format,
+         .color_is_int8 = pipeline_key->ps.color_is_int8,
+         .color_is_int10 = pipeline_key->ps.color_is_int10,
          .enable_mrt_output_nan_fixup = pipeline_key->ps.enable_mrt_output_nan_fixup,
          .mrt0_is_dual_src = pipeline_key->ps.mrt0_is_dual_src,
       };
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index 13c5104225f..011181d885a 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -85,9 +85,9 @@ struct radv_pipeline_key {
    } tcs;
 
    struct {
-      uint32_t col_format;
-      uint32_t is_int8;
-      uint32_t is_int10;
+      uint32_t spi_shader_col_format;
+      uint32_t color_is_int8;
+      uint32_t color_is_int10;
       uint32_t cb_target_mask;
       uint8_t num_samples;
       bool sample_shading_enable;