diff --git a/src/amd/compiler/README-ISA.md b/src/amd/compiler/README-ISA.md
index a790522ba4f..cb9d8da0298 100644
--- a/src/amd/compiler/README-ISA.md
+++ b/src/amd/compiler/README-ISA.md
@@ -250,3 +250,8 @@ Only `s_waitcnt_vscnt null, 0`. Needed even if the first instruction is a load.
 ### NSAClauseBug
 
 "MIMG-NSA in a hard clause has unpredictable results on GFX10.1"
+
+### NSAMaxSize5
+
+NSA MIMG instructions should be limited to 3 dwords before GFX10.3 to avoid
+stability issues: https://reviews.llvm.org/D103348
diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp
index 4c0c8871446..3428bd1518f 100644
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -5544,7 +5544,11 @@ static MIMG_instruction *emit_mimg(Builder& bld, aco_opcode op,
                                    unsigned wqm_mask=0,
                                    Operand vdata=Operand(v1))
 {
-   if (bld.program->chip_class < GFX10) {
+   /* Limit NSA instructions to 3 dwords on GFX10 to avoid stability issues. */
+   unsigned max_nsa_size = bld.program->chip_class >= GFX10_3 ? 13 : 5;
+   bool use_nsa = bld.program->chip_class >= GFX10 && coords.size() <= max_nsa_size;
+
+   if (!use_nsa) {
       Temp coord = coords[0];
       if (coords.size() > 1) {
          coord = bld.tmp(RegType::vgpr, coords.size());