intel/compiler: validate region restrictions for mixed float mode
v2: - Adapted unit tests to make them consistent with the changes done to the validation of half-float conversions. v3 (Curro): - Check all the accummulators - Constify declarations - Do not check src1 type in single-source instructions. - Check for all instructions that read accumulator (either implicitly or explicitly) - Check restrictions in src1 too. - Merge conditional block - Add invalid test case. v4 (Curro): - Assert on 3-src instructions, as they are not validated. - Get rid of types_are_mixed_float(), as we know instruction is mixed float at that point. - Remove conditions from not verified case. - Fix brackets on conditional. Reviewed-by: Francisco Jerez <currojerez@riseup.net>
This commit is contained in:
Iago Toral Quiroga
committed by
Juan A. Suarez Romero
Juan A. Suarez Romero
parent
58d6417e59
commit
8ed6d74c92
@@ -1019,6 +1019,636 @@ TEST_P(validation_test, half_float_conversion)
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}
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}
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TEST_P(validation_test, mixed_float_source_indirect_addressing)
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{
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static const struct {
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enum brw_reg_type dst_type;
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enum brw_reg_type src0_type;
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enum brw_reg_type src1_type;
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unsigned dst_stride;
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bool dst_indirect;
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bool src0_indirect;
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bool expected_result;
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} inst[] = {
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#define INST(dst_type, src0_type, src1_type, \
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dst_stride, dst_indirect, src0_indirect, expected_result) \
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{ \
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BRW_REGISTER_TYPE_##dst_type, \
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BRW_REGISTER_TYPE_##src0_type, \
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BRW_REGISTER_TYPE_##src1_type, \
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BRW_HORIZONTAL_STRIDE_##dst_stride, \
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dst_indirect, \
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src0_indirect, \
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expected_result, \
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}
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/* Source and dest are mixed float: indirect src addressing not allowed */
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INST(HF, F, F, 2, false, false, true),
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INST(HF, F, F, 2, true, false, true),
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INST(HF, F, F, 2, false, true, false),
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INST(HF, F, F, 2, true, true, false),
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INST( F, HF, F, 1, false, false, true),
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INST( F, HF, F, 1, true, false, true),
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INST( F, HF, F, 1, false, true, false),
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INST( F, HF, F, 1, true, true, false),
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INST(HF, HF, F, 2, false, false, true),
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INST(HF, HF, F, 2, true, false, true),
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INST(HF, HF, F, 2, false, true, false),
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INST(HF, HF, F, 2, true, true, false),
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INST( F, F, HF, 1, false, false, true),
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INST( F, F, HF, 1, true, false, true),
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INST( F, F, HF, 1, false, true, false),
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INST( F, F, HF, 1, true, true, false),
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#undef INST
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};
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if (devinfo.gen < 8)
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return;
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for (unsigned i = 0; i < sizeof(inst) / sizeof(inst[0]); i++) {
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brw_ADD(p, retype(g0, inst[i].dst_type),
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retype(g0, inst[i].src0_type),
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retype(g0, inst[i].src1_type));
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brw_inst_set_dst_address_mode(&devinfo, last_inst, inst[i].dst_indirect);
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brw_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride);
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brw_inst_set_src0_address_mode(&devinfo, last_inst, inst[i].src0_indirect);
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EXPECT_EQ(inst[i].expected_result, validate(p));
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clear_instructions(p);
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}
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}
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TEST_P(validation_test, mixed_float_align1_simd16)
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{
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static const struct {
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unsigned exec_size;
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enum brw_reg_type dst_type;
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enum brw_reg_type src0_type;
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enum brw_reg_type src1_type;
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unsigned dst_stride;
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bool expected_result;
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} inst[] = {
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#define INST(exec_size, dst_type, src0_type, src1_type, \
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dst_stride, expected_result) \
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{ \
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BRW_EXECUTE_##exec_size, \
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BRW_REGISTER_TYPE_##dst_type, \
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BRW_REGISTER_TYPE_##src0_type, \
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BRW_REGISTER_TYPE_##src1_type, \
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BRW_HORIZONTAL_STRIDE_##dst_stride, \
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expected_result, \
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}
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/* No SIMD16 in mixed mode when destination is packed f16 */
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INST( 8, HF, F, HF, 2, true),
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INST(16, HF, HF, F, 2, true),
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INST(16, HF, HF, F, 1, false),
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INST(16, HF, F, HF, 1, false),
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/* No SIMD16 in mixed mode when destination is f32 */
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INST( 8, F, HF, F, 1, true),
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INST( 8, F, F, HF, 1, true),
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INST(16, F, HF, F, 1, false),
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INST(16, F, F, HF, 1, false),
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#undef INST
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};
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if (devinfo.gen < 8)
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return;
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for (unsigned i = 0; i < sizeof(inst) / sizeof(inst[0]); i++) {
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brw_ADD(p, retype(g0, inst[i].dst_type),
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retype(g0, inst[i].src0_type),
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retype(g0, inst[i].src1_type));
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brw_inst_set_exec_size(&devinfo, last_inst, inst[i].exec_size);
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brw_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride);
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EXPECT_EQ(inst[i].expected_result, validate(p));
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clear_instructions(p);
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}
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}
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TEST_P(validation_test, mixed_float_align1_packed_fp16_dst_acc_read_offset_0)
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{
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static const struct {
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enum brw_reg_type dst_type;
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enum brw_reg_type src0_type;
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enum brw_reg_type src1_type;
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unsigned dst_stride;
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bool read_acc;
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unsigned subnr;
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bool expected_result_bdw;
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bool expected_result_chv_skl;
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} inst[] = {
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#define INST(dst_type, src0_type, src1_type, dst_stride, read_acc, subnr, \
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expected_result_bdw, expected_result_chv_skl) \
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{ \
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BRW_REGISTER_TYPE_##dst_type, \
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BRW_REGISTER_TYPE_##src0_type, \
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BRW_REGISTER_TYPE_##src1_type, \
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BRW_HORIZONTAL_STRIDE_##dst_stride, \
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read_acc, \
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subnr, \
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expected_result_bdw, \
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expected_result_chv_skl, \
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}
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/* Destination is not packed */
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INST(HF, HF, F, 2, true, 0, true, true),
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INST(HF, HF, F, 2, true, 2, true, true),
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INST(HF, HF, F, 2, true, 4, true, true),
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INST(HF, HF, F, 2, true, 8, true, true),
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INST(HF, HF, F, 2, true, 16, true, true),
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/* Destination is packed, we don't read acc */
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INST(HF, HF, F, 1, false, 0, false, true),
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INST(HF, HF, F, 1, false, 2, false, true),
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INST(HF, HF, F, 1, false, 4, false, true),
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INST(HF, HF, F, 1, false, 8, false, true),
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INST(HF, HF, F, 1, false, 16, false, true),
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/* Destination is packed, we read acc */
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INST(HF, HF, F, 1, true, 0, false, false),
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INST(HF, HF, F, 1, true, 2, false, false),
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INST(HF, HF, F, 1, true, 4, false, false),
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INST(HF, HF, F, 1, true, 8, false, false),
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INST(HF, HF, F, 1, true, 16, false, false),
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#undef INST
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};
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if (devinfo.gen < 8)
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return;
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for (unsigned i = 0; i < sizeof(inst) / sizeof(inst[0]); i++) {
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brw_ADD(p, retype(g0, inst[i].dst_type),
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retype(inst[i].read_acc ? acc0 : g0, inst[i].src0_type),
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retype(g0, inst[i].src1_type));
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brw_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride);
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brw_inst_set_src0_da1_subreg_nr(&devinfo, last_inst, inst[i].subnr);
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if (devinfo.is_cherryview || devinfo.gen >= 9)
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EXPECT_EQ(inst[i].expected_result_chv_skl, validate(p));
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else
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EXPECT_EQ(inst[i].expected_result_bdw, validate(p));
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clear_instructions(p);
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}
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}
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TEST_P(validation_test, mixed_float_fp16_dest_with_acc)
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{
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static const struct {
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unsigned exec_size;
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unsigned opcode;
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enum brw_reg_type dst_type;
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enum brw_reg_type src0_type;
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enum brw_reg_type src1_type;
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unsigned dst_stride;
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bool read_acc;
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bool expected_result_bdw;
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bool expected_result_chv_skl;
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} inst[] = {
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#define INST(exec_size, opcode, dst_type, src0_type, src1_type, \
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dst_stride, read_acc,expected_result_bdw, \
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expected_result_chv_skl) \
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{ \
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BRW_EXECUTE_##exec_size, \
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BRW_OPCODE_##opcode, \
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BRW_REGISTER_TYPE_##dst_type, \
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BRW_REGISTER_TYPE_##src0_type, \
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BRW_REGISTER_TYPE_##src1_type, \
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BRW_HORIZONTAL_STRIDE_##dst_stride, \
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read_acc, \
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expected_result_bdw, \
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expected_result_chv_skl, \
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}
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/* Packed fp16 dest with implicit acc needs hstride=2 */
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INST(8, MAC, HF, HF, F, 1, false, false, false),
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INST(8, MAC, HF, HF, F, 2, false, true, true),
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INST(8, MAC, HF, F, HF, 1, false, false, false),
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INST(8, MAC, HF, F, HF, 2, false, true, true),
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/* Packed fp16 dest with explicit acc needs hstride=2 */
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INST(8, ADD, HF, HF, F, 1, true, false, false),
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INST(8, ADD, HF, HF, F, 2, true, true, true),
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INST(8, ADD, HF, F, HF, 1, true, false, false),
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INST(8, ADD, HF, F, HF, 2, true, true, true),
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/* If destination is not fp16, restriction doesn't apply */
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INST(8, MAC, F, HF, F, 1, false, true, true),
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INST(8, MAC, F, HF, F, 2, false, true, true),
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/* If there is no implicit/explicit acc, restriction doesn't apply */
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INST(8, ADD, HF, HF, F, 1, false, false, true),
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INST(8, ADD, HF, HF, F, 2, false, true, true),
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INST(8, ADD, HF, F, HF, 1, false, false, true),
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INST(8, ADD, HF, F, HF, 2, false, true, true),
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INST(8, ADD, F, HF, F, 1, false, true, true),
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INST(8, ADD, F, HF, F, 2, false, true, true),
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#undef INST
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};
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if (devinfo.gen < 8)
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return;
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for (unsigned i = 0; i < sizeof(inst) / sizeof(inst[0]); i++) {
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if (inst[i].opcode == BRW_OPCODE_MAC) {
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brw_MAC(p, retype(g0, inst[i].dst_type),
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retype(g0, inst[i].src0_type),
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retype(g0, inst[i].src1_type));
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} else {
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assert(inst[i].opcode == BRW_OPCODE_ADD);
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brw_ADD(p, retype(g0, inst[i].dst_type),
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retype(inst[i].read_acc ? acc0: g0, inst[i].src0_type),
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retype(g0, inst[i].src1_type));
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}
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brw_inst_set_exec_size(&devinfo, last_inst, inst[i].exec_size);
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brw_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride);
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if (devinfo.is_cherryview || devinfo.gen >= 9)
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EXPECT_EQ(inst[i].expected_result_chv_skl, validate(p));
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else
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EXPECT_EQ(inst[i].expected_result_bdw, validate(p));
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clear_instructions(p);
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}
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}
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TEST_P(validation_test, mixed_float_align1_math_strided_fp16_inputs)
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{
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static const struct {
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enum brw_reg_type dst_type;
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enum brw_reg_type src0_type;
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enum brw_reg_type src1_type;
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unsigned dst_stride;
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unsigned src0_stride;
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unsigned src1_stride;
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bool expected_result;
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} inst[] = {
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#define INST(dst_type, src0_type, src1_type, \
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dst_stride, src0_stride, src1_stride, expected_result) \
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{ \
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BRW_REGISTER_TYPE_##dst_type, \
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BRW_REGISTER_TYPE_##src0_type, \
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BRW_REGISTER_TYPE_##src1_type, \
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BRW_HORIZONTAL_STRIDE_##dst_stride, \
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BRW_HORIZONTAL_STRIDE_##src0_stride, \
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BRW_HORIZONTAL_STRIDE_##src1_stride, \
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expected_result, \
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}
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INST(HF, HF, F, 2, 2, 1, true),
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INST(HF, F, HF, 2, 1, 2, true),
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INST(HF, F, HF, 1, 1, 2, true),
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INST(HF, F, HF, 2, 1, 1, false),
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INST(HF, HF, F, 2, 1, 1, false),
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INST(HF, HF, F, 1, 1, 1, false),
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INST(HF, HF, F, 2, 1, 1, false),
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INST( F, HF, F, 1, 1, 1, false),
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INST( F, F, HF, 1, 1, 2, true),
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INST( F, HF, HF, 1, 2, 1, false),
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INST( F, HF, HF, 1, 2, 2, true),
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#undef INST
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};
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/* No half-float math in gen8 */
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if (devinfo.gen < 9)
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return;
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for (unsigned i = 0; i < sizeof(inst) / sizeof(inst[0]); i++) {
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gen6_math(p, retype(g0, inst[i].dst_type),
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BRW_MATH_FUNCTION_POW,
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retype(g0, inst[i].src0_type),
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retype(g0, inst[i].src1_type));
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brw_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride);
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brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
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brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_4);
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brw_inst_set_src0_hstride(&devinfo, last_inst, inst[i].src0_stride);
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brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
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brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_4);
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brw_inst_set_src1_hstride(&devinfo, last_inst, inst[i].src1_stride);
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EXPECT_EQ(inst[i].expected_result, validate(p));
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clear_instructions(p);
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}
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}
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TEST_P(validation_test, mixed_float_align1_packed_fp16_dst)
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{
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static const struct {
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unsigned exec_size;
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enum brw_reg_type dst_type;
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enum brw_reg_type src0_type;
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enum brw_reg_type src1_type;
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unsigned dst_stride;
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unsigned dst_subnr;
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bool expected_result_bdw;
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bool expected_result_chv_skl;
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} inst[] = {
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#define INST(exec_size, dst_type, src0_type, src1_type, dst_stride, dst_subnr, \
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expected_result_bdw, expected_result_chv_skl) \
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{ \
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BRW_EXECUTE_##exec_size, \
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BRW_REGISTER_TYPE_##dst_type, \
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BRW_REGISTER_TYPE_##src0_type, \
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BRW_REGISTER_TYPE_##src1_type, \
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BRW_HORIZONTAL_STRIDE_##dst_stride, \
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dst_subnr, \
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expected_result_bdw, \
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expected_result_chv_skl \
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}
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/* SIMD8 packed fp16 dst won't cross oword boundaries if region is
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* oword-aligned
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*/
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INST( 8, HF, HF, F, 1, 0, false, true),
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INST( 8, HF, HF, F, 1, 2, false, false),
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INST( 8, HF, HF, F, 1, 4, false, false),
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INST( 8, HF, HF, F, 1, 8, false, false),
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INST( 8, HF, HF, F, 1, 16, false, true),
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/* SIMD16 packed fp16 always crosses oword boundaries */
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INST(16, HF, HF, F, 1, 0, false, false),
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INST(16, HF, HF, F, 1, 2, false, false),
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INST(16, HF, HF, F, 1, 4, false, false),
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INST(16, HF, HF, F, 1, 8, false, false),
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INST(16, HF, HF, F, 1, 16, false, false),
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/* If destination is not packed (or not fp16) we can cross oword
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* boundaries
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*/
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INST( 8, HF, HF, F, 2, 0, true, true),
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INST( 8, F, HF, F, 1, 0, true, true),
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#undef INST
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};
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if (devinfo.gen < 8)
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return;
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for (unsigned i = 0; i < sizeof(inst) / sizeof(inst[0]); i++) {
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brw_ADD(p, retype(g0, inst[i].dst_type),
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retype(g0, inst[i].src0_type),
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retype(g0, inst[i].src1_type));
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brw_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride);
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brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, inst[i].dst_subnr);
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brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
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brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_4);
|
||||
brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
|
||||
|
||||
brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
|
||||
brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_4);
|
||||
brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
|
||||
|
||||
brw_inst_set_exec_size(&devinfo, last_inst, inst[i].exec_size);
|
||||
|
||||
if (devinfo.is_cherryview || devinfo.gen >= 9)
|
||||
EXPECT_EQ(inst[i].expected_result_chv_skl, validate(p));
|
||||
else
|
||||
EXPECT_EQ(inst[i].expected_result_bdw, validate(p));
|
||||
|
||||
clear_instructions(p);
|
||||
}
|
||||
}
|
||||
|
||||
TEST_P(validation_test, mixed_float_align16_packed_data)
|
||||
{
|
||||
static const struct {
|
||||
enum brw_reg_type dst_type;
|
||||
enum brw_reg_type src0_type;
|
||||
enum brw_reg_type src1_type;
|
||||
unsigned src0_vstride;
|
||||
unsigned src1_vstride;
|
||||
bool expected_result;
|
||||
} inst[] = {
|
||||
#define INST(dst_type, src0_type, src1_type, \
|
||||
src0_vstride, src1_vstride, expected_result) \
|
||||
{ \
|
||||
BRW_REGISTER_TYPE_##dst_type, \
|
||||
BRW_REGISTER_TYPE_##src0_type, \
|
||||
BRW_REGISTER_TYPE_##src1_type, \
|
||||
BRW_VERTICAL_STRIDE_##src0_vstride, \
|
||||
BRW_VERTICAL_STRIDE_##src1_vstride, \
|
||||
expected_result, \
|
||||
}
|
||||
|
||||
/* We only test with F destination because there is a restriction
|
||||
* by which F->HF conversions need to be DWord aligned but Align16 also
|
||||
* requires that destination horizontal stride is 1.
|
||||
*/
|
||||
INST(F, F, HF, 4, 4, true),
|
||||
INST(F, F, HF, 2, 4, false),
|
||||
INST(F, F, HF, 4, 2, false),
|
||||
INST(F, F, HF, 0, 4, false),
|
||||
INST(F, F, HF, 4, 0, false),
|
||||
INST(F, HF, F, 4, 4, true),
|
||||
INST(F, HF, F, 4, 2, false),
|
||||
INST(F, HF, F, 2, 4, false),
|
||||
INST(F, HF, F, 0, 4, false),
|
||||
INST(F, HF, F, 4, 0, false),
|
||||
|
||||
#undef INST
|
||||
};
|
||||
|
||||
if (devinfo.gen < 8 || devinfo.gen >= 11)
|
||||
return;
|
||||
|
||||
brw_set_default_access_mode(p, BRW_ALIGN_16);
|
||||
|
||||
for (unsigned i = 0; i < sizeof(inst) / sizeof(inst[0]); i++) {
|
||||
brw_ADD(p, retype(g0, inst[i].dst_type),
|
||||
retype(g0, inst[i].src0_type),
|
||||
retype(g0, inst[i].src1_type));
|
||||
|
||||
brw_inst_set_src0_vstride(&devinfo, last_inst, inst[i].src0_vstride);
|
||||
brw_inst_set_src1_vstride(&devinfo, last_inst, inst[i].src1_vstride);
|
||||
|
||||
EXPECT_EQ(inst[i].expected_result, validate(p));
|
||||
|
||||
clear_instructions(p);
|
||||
}
|
||||
}
|
||||
|
||||
TEST_P(validation_test, mixed_float_align16_no_simd16)
|
||||
{
|
||||
static const struct {
|
||||
unsigned exec_size;
|
||||
enum brw_reg_type dst_type;
|
||||
enum brw_reg_type src0_type;
|
||||
enum brw_reg_type src1_type;
|
||||
bool expected_result;
|
||||
} inst[] = {
|
||||
#define INST(exec_size, dst_type, src0_type, src1_type, expected_result) \
|
||||
{ \
|
||||
BRW_EXECUTE_##exec_size, \
|
||||
BRW_REGISTER_TYPE_##dst_type, \
|
||||
BRW_REGISTER_TYPE_##src0_type, \
|
||||
BRW_REGISTER_TYPE_##src1_type, \
|
||||
expected_result, \
|
||||
}
|
||||
|
||||
/* We only test with F destination because there is a restriction
|
||||
* by which F->HF conversions need to be DWord aligned but Align16 also
|
||||
* requires that destination horizontal stride is 1.
|
||||
*/
|
||||
INST( 8, F, F, HF, true),
|
||||
INST( 8, F, HF, F, true),
|
||||
INST( 8, F, F, HF, true),
|
||||
INST(16, F, F, HF, false),
|
||||
INST(16, F, HF, F, false),
|
||||
INST(16, F, F, HF, false),
|
||||
|
||||
#undef INST
|
||||
};
|
||||
|
||||
if (devinfo.gen < 8 || devinfo.gen >= 11)
|
||||
return;
|
||||
|
||||
brw_set_default_access_mode(p, BRW_ALIGN_16);
|
||||
|
||||
for (unsigned i = 0; i < sizeof(inst) / sizeof(inst[0]); i++) {
|
||||
brw_ADD(p, retype(g0, inst[i].dst_type),
|
||||
retype(g0, inst[i].src0_type),
|
||||
retype(g0, inst[i].src1_type));
|
||||
|
||||
brw_inst_set_exec_size(&devinfo, last_inst, inst[i].exec_size);
|
||||
|
||||
brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
|
||||
brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
|
||||
|
||||
EXPECT_EQ(inst[i].expected_result, validate(p));
|
||||
|
||||
clear_instructions(p);
|
||||
}
|
||||
}
|
||||
|
||||
TEST_P(validation_test, mixed_float_align16_no_acc_read)
|
||||
{
|
||||
static const struct {
|
||||
enum brw_reg_type dst_type;
|
||||
enum brw_reg_type src0_type;
|
||||
enum brw_reg_type src1_type;
|
||||
bool read_acc;
|
||||
bool expected_result;
|
||||
} inst[] = {
|
||||
#define INST(dst_type, src0_type, src1_type, read_acc, expected_result) \
|
||||
{ \
|
||||
BRW_REGISTER_TYPE_##dst_type, \
|
||||
BRW_REGISTER_TYPE_##src0_type, \
|
||||
BRW_REGISTER_TYPE_##src1_type, \
|
||||
read_acc, \
|
||||
expected_result, \
|
||||
}
|
||||
|
||||
/* We only test with F destination because there is a restriction
|
||||
* by which F->HF conversions need to be DWord aligned but Align16 also
|
||||
* requires that destination horizontal stride is 1.
|
||||
*/
|
||||
INST( F, F, HF, false, true),
|
||||
INST( F, F, HF, true, false),
|
||||
INST( F, HF, F, false, true),
|
||||
INST( F, HF, F, true, false),
|
||||
|
||||
#undef INST
|
||||
};
|
||||
|
||||
if (devinfo.gen < 8 || devinfo.gen >= 11)
|
||||
return;
|
||||
|
||||
brw_set_default_access_mode(p, BRW_ALIGN_16);
|
||||
|
||||
for (unsigned i = 0; i < sizeof(inst) / sizeof(inst[0]); i++) {
|
||||
brw_ADD(p, retype(g0, inst[i].dst_type),
|
||||
retype(inst[i].read_acc ? acc0 : g0, inst[i].src0_type),
|
||||
retype(g0, inst[i].src1_type));
|
||||
|
||||
brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
|
||||
brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
|
||||
|
||||
EXPECT_EQ(inst[i].expected_result, validate(p));
|
||||
|
||||
clear_instructions(p);
|
||||
}
|
||||
}
|
||||
|
||||
TEST_P(validation_test, mixed_float_align16_math_packed_format)
|
||||
{
|
||||
static const struct {
|
||||
enum brw_reg_type dst_type;
|
||||
enum brw_reg_type src0_type;
|
||||
enum brw_reg_type src1_type;
|
||||
unsigned src0_vstride;
|
||||
unsigned src1_vstride;
|
||||
bool expected_result;
|
||||
} inst[] = {
|
||||
#define INST(dst_type, src0_type, src1_type, \
|
||||
src0_vstride, src1_vstride, expected_result) \
|
||||
{ \
|
||||
BRW_REGISTER_TYPE_##dst_type, \
|
||||
BRW_REGISTER_TYPE_##src0_type, \
|
||||
BRW_REGISTER_TYPE_##src1_type, \
|
||||
BRW_VERTICAL_STRIDE_##src0_vstride, \
|
||||
BRW_VERTICAL_STRIDE_##src1_vstride, \
|
||||
expected_result, \
|
||||
}
|
||||
|
||||
/* We only test with F destination because there is a restriction
|
||||
* by which F->HF conversions need to be DWord aligned but Align16 also
|
||||
* requires that destination horizontal stride is 1.
|
||||
*/
|
||||
INST( F, HF, F, 4, 0, false),
|
||||
INST( F, HF, HF, 4, 4, true),
|
||||
INST( F, F, HF, 4, 0, false),
|
||||
INST( F, F, HF, 2, 4, false),
|
||||
INST( F, F, HF, 4, 2, false),
|
||||
INST( F, HF, HF, 0, 4, false),
|
||||
|
||||
#undef INST
|
||||
};
|
||||
|
||||
/* Align16 Math for mixed float mode is not supported in gen8 */
|
||||
if (devinfo.gen < 9 || devinfo.gen >= 11)
|
||||
return;
|
||||
|
||||
brw_set_default_access_mode(p, BRW_ALIGN_16);
|
||||
|
||||
for (unsigned i = 0; i < sizeof(inst) / sizeof(inst[0]); i++) {
|
||||
gen6_math(p, retype(g0, inst[i].dst_type),
|
||||
BRW_MATH_FUNCTION_POW,
|
||||
retype(g0, inst[i].src0_type),
|
||||
retype(g0, inst[i].src1_type));
|
||||
|
||||
brw_inst_set_src0_vstride(&devinfo, last_inst, inst[i].src0_vstride);
|
||||
brw_inst_set_src1_vstride(&devinfo, last_inst, inst[i].src1_vstride);
|
||||
|
||||
EXPECT_EQ(inst[i].expected_result, validate(p));
|
||||
|
||||
clear_instructions(p);
|
||||
}
|
||||
}
|
||||
|
||||
TEST_P(validation_test, vector_immediate_destination_alignment)
|
||||
{
|
||||
static const struct {
|
||||
|
||||
Reference in New Issue
Block a user