diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h
index b480dacbe8e..019dac345d7 100644
--- a/src/intel/compiler/brw_fs.h
+++ b/src/intel/compiler/brw_fs.h
@@ -330,7 +330,8 @@ public:
    void emit_urb_fence();
    void emit_cs_terminate();
 
-   fs_reg interp_reg(int location, int channel);
+   fs_reg interp_reg(const brw::fs_builder &bld, unsigned location,
+                     unsigned channel, unsigned comp);
    fs_reg per_primitive_reg(int location, unsigned comp);
 
    virtual void dump_instruction_to_file(const backend_instruction *inst, FILE *file) const;
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 3cd6efd7592..819ab825df5 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -3534,7 +3534,7 @@ emit_fragcoord_interpolation(nir_to_brw_state &ntb, fs_reg wpos)
    } else {
       bld.emit(FS_OPCODE_LINTERP, wpos,
                s.delta_xy[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL],
-               component(s.interp_reg(VARYING_SLOT_POS, 2), 0));
+               s.interp_reg(bld, VARYING_SLOT_POS, 2, 0));
    }
    wpos = offset(wpos, bld, 1);
 
@@ -4113,7 +4113,7 @@ fs_nir_emit_fs_intrinsic(nir_to_brw_state &ntb,
       } else {
          for (unsigned int i = 0; i < num_components; i++) {
             bld.MOV(offset(dest, bld, i),
-                    retype(component(s.interp_reg(base, comp + i), 3), dest.type));
+                    retype(s.interp_reg(bld, base, comp + i, 3), dest.type));
          }
       }
       break;
@@ -4122,12 +4122,12 @@ fs_nir_emit_fs_intrinsic(nir_to_brw_state &ntb,
    case nir_intrinsic_load_fs_input_interp_deltas: {
       assert(s.stage == MESA_SHADER_FRAGMENT);
       assert(nir_src_as_uint(instr->src[0]) == 0);
-      fs_reg interp = s.interp_reg(nir_intrinsic_base(instr),
-                                    nir_intrinsic_component(instr));
+      const unsigned base = nir_intrinsic_base(instr);
+      const unsigned comp = nir_intrinsic_component(instr);
       dest.type = BRW_REGISTER_TYPE_F;
-      bld.MOV(offset(dest, bld, 0), component(interp, 3));
-      bld.MOV(offset(dest, bld, 1), component(interp, 1));
-      bld.MOV(offset(dest, bld, 2), component(interp, 0));
+      bld.MOV(offset(dest, bld, 0), s.interp_reg(bld, base, comp, 3));
+      bld.MOV(offset(dest, bld, 1), s.interp_reg(bld, base, comp, 1));
+      bld.MOV(offset(dest, bld, 2), s.interp_reg(bld, base, comp, 0));
       break;
    }
 
@@ -4236,8 +4236,8 @@ fs_nir_emit_fs_intrinsic(nir_to_brw_state &ntb,
 
       for (unsigned int i = 0; i < instr->num_components; i++) {
          fs_reg interp =
-            component(s.interp_reg(nir_intrinsic_base(instr),
-                                    nir_intrinsic_component(instr) + i), 0);
+            s.interp_reg(bld, nir_intrinsic_base(instr),
+                         nir_intrinsic_component(instr) + i, 0);
          interp.type = BRW_REGISTER_TYPE_F;
          dest.type = BRW_REGISTER_TYPE_F;
 
diff --git a/src/intel/compiler/brw_fs_visitor.cpp b/src/intel/compiler/brw_fs_visitor.cpp
index fb90df28338..88985521fd2 100644
--- a/src/intel/compiler/brw_fs_visitor.cpp
+++ b/src/intel/compiler/brw_fs_visitor.cpp
@@ -45,7 +45,8 @@ using namespace brw;
  * generate_code() time.
  */
 fs_reg
-fs_visitor::interp_reg(int location, int channel)
+fs_visitor::interp_reg(const fs_builder &bld, unsigned location,
+                       unsigned channel, unsigned comp)
 {
    assert(stage == MESA_SHADER_FRAGMENT);
    assert(BITFIELD64_BIT(location) & ~nir->info.per_primitive_inputs);
@@ -63,7 +64,7 @@ fs_visitor::interp_reg(int location, int channel)
    const unsigned per_vertex_start = prog_data->num_per_primitive_inputs;
    const unsigned regnr = per_vertex_start + (nr * 4) + channel;
 
-   return fs_reg(ATTR, regnr, BRW_REGISTER_TYPE_F);
+   return component(fs_reg(ATTR, regnr, BRW_REGISTER_TYPE_F), comp);
 }
 
 /* The register location here is relative to the start of the URB
@@ -143,7 +144,7 @@ fs_visitor::emit_interpolation_setup_gfx4()
     */
    this->wpos_w = vgrf(glsl_float_type());
    abld.emit(FS_OPCODE_LINTERP, wpos_w, delta_xy,
-             component(interp_reg(VARYING_SLOT_POS, 3), 0));
+             interp_reg(abld, VARYING_SLOT_POS, 3, 0));
    /* Compute the pixel 1/W value from wpos.w. */
    this->pixel_w = vgrf(glsl_float_type());
    abld.emit(SHADER_OPCODE_RCP, this->pixel_w, wpos_w);