diff --git a/src/intel/compiler/brw_builder.h b/src/intel/compiler/brw_builder.h index 5e9eb977038..9df8bd2138e 100644 --- a/src/intel/compiler/brw_builder.h +++ b/src/intel/compiler/brw_builder.h @@ -37,8 +37,10 @@ static inline brw_reg offset(const brw_reg &, const brw_builder &, class brw_builder { public: /** - * Construct an brw_builder that inserts instructions into \p shader. - * \p dispatch_width gives the native execution width of the program. + * Construct an brw_builder that inserts instructions + * at the end of \p shader. The \p dispatch_width gives + * the execution width, that may differ from the shader + * dispatch_width. */ brw_builder(brw_shader *shader, unsigned dispatch_width) : @@ -48,6 +50,8 @@ public: force_writemask_all(false), annotation() { + if (shader) + cursor = (exec_node *)&shader->instructions.tail_sentinel; } /** @@ -92,17 +96,6 @@ public: return bld; } - /** - * Construct an brw_builder appending instructions at the end of the - * instruction list of the shader, inheriting other code generation - * parameters from this. - */ - brw_builder - at_end() const - { - return at(NULL, (exec_node *)&shader->instructions.tail_sentinel); - } - /** * Construct a builder specifying the default SIMD width and group of * channel enable signals, inheriting other code generation parameters diff --git a/src/intel/compiler/brw_compile_cs.cpp b/src/intel/compiler/brw_compile_cs.cpp index b72b1701668..122ca450d80 100644 --- a/src/intel/compiler/brw_compile_cs.cpp +++ b/src/intel/compiler/brw_compile_cs.cpp @@ -62,7 +62,7 @@ static bool run_cs(brw_shader &s, bool allow_spilling) { assert(gl_shader_stage_is_compute(s.stage)); - const brw_builder bld = brw_builder(&s).at_end(); + const brw_builder bld = brw_builder(&s); s.payload_ = new brw_cs_thread_payload(s); diff --git a/src/intel/compiler/brw_compile_fs.cpp b/src/intel/compiler/brw_compile_fs.cpp index 5265a2b5763..fbdd9e058bb 100644 --- a/src/intel/compiler/brw_compile_fs.cpp +++ b/src/intel/compiler/brw_compile_fs.cpp @@ -58,7 +58,7 @@ brw_emit_single_fb_write(brw_shader &s, const brw_builder &bld, static void brw_do_emit_fb_writes(brw_shader &s, int nr_color_regions, bool replicate_alpha) { - const brw_builder bld = brw_builder(&s).at_end(); + const brw_builder bld = brw_builder(&s); brw_inst *inst = NULL; for (int target = 0; target < nr_color_regions; target++) { @@ -179,7 +179,7 @@ static void brw_emit_interpolation_setup(brw_shader &s) { const struct intel_device_info *devinfo = s.devinfo; - const brw_builder bld = brw_builder(&s).at_end(); + const brw_builder bld = brw_builder(&s); brw_builder abld = bld.annotate("compute pixel centers"); s.pixel_x = bld.vgrf(BRW_TYPE_F); @@ -618,7 +618,7 @@ brw_emit_repclear_shader(brw_shader &s) BRW_VERTICAL_STRIDE_8, BRW_WIDTH_2, BRW_HORIZONTAL_STRIDE_4, BRW_SWIZZLE_XYZW, WRITEMASK_XYZW); - const brw_builder bld = brw_builder(&s).at_end(); + const brw_builder bld = brw_builder(&s); bld.exec_all().group(4, 0).MOV(color_output, color_input); if (key->nr_color_regions > 1) { @@ -1454,7 +1454,7 @@ run_fs(brw_shader &s, bool allow_spilling, bool do_rep_send) const struct intel_device_info *devinfo = s.devinfo; struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(s.prog_data); brw_wm_prog_key *wm_key = (brw_wm_prog_key *) s.key; - const brw_builder bld = brw_builder(&s).at_end(); + const brw_builder bld = brw_builder(&s); const nir_shader *nir = s.nir; assert(s.stage == MESA_SHADER_FRAGMENT); diff --git a/src/intel/compiler/brw_compile_gs.cpp b/src/intel/compiler/brw_compile_gs.cpp index 347ecbd14b2..7ac66d683bd 100644 --- a/src/intel/compiler/brw_compile_gs.cpp +++ b/src/intel/compiler/brw_compile_gs.cpp @@ -40,7 +40,7 @@ brw_emit_gs_thread_end(brw_shader &s) s.emit_gs_control_data_bits(s.final_gs_vertex_count); } - const brw_builder abld = brw_builder(&s).at_end().annotate("thread end"); + const brw_builder abld = brw_builder(&s).annotate("thread end"); brw_inst *inst; if (gs_prog_data->static_vertex_count != -1) { @@ -90,7 +90,7 @@ run_gs(brw_shader &s) s.payload_ = new brw_gs_thread_payload(s); - const brw_builder bld = brw_builder(&s).at_end(); + const brw_builder bld = brw_builder(&s); s.final_gs_vertex_count = bld.vgrf(BRW_TYPE_UD); diff --git a/src/intel/compiler/brw_compile_mesh.cpp b/src/intel/compiler/brw_compile_mesh.cpp index 79794a80a5d..4c65d569a5e 100644 --- a/src/intel/compiler/brw_compile_mesh.cpp +++ b/src/intel/compiler/brw_compile_mesh.cpp @@ -289,7 +289,7 @@ brw_nir_lower_mesh_primitive_count(nir_shader *nir) static void brw_emit_urb_fence(brw_shader &s) { - const brw_builder bld1 = brw_builder(&s).at_end().exec_all().group(1, 0); + const brw_builder bld1 = brw_builder(&s).exec_all().group(1, 0); brw_reg dst = bld1.vgrf(BRW_TYPE_UD); brw_inst *fence = bld1.emit(SHADER_OPCODE_MEMORY_FENCE, dst, brw_vec8_grf(0, 0), diff --git a/src/intel/compiler/brw_compile_tcs.cpp b/src/intel/compiler/brw_compile_tcs.cpp index efa3ac2cdf5..417f2e015ca 100644 --- a/src/intel/compiler/brw_compile_tcs.cpp +++ b/src/intel/compiler/brw_compile_tcs.cpp @@ -47,7 +47,7 @@ brw_set_tcs_invocation_id(brw_shader &s) const struct intel_device_info *devinfo = s.devinfo; struct brw_tcs_prog_data *tcs_prog_data = brw_tcs_prog_data(s.prog_data); struct brw_vue_prog_data *vue_prog_data = &tcs_prog_data->base; - const brw_builder bld = brw_builder(&s).at_end(); + const brw_builder bld = brw_builder(&s); const unsigned instance_id_mask = (devinfo->verx10 >= 125) ? INTEL_MASK(7, 0) : @@ -97,7 +97,7 @@ brw_emit_tcs_thread_end(brw_shader &s) if (s.mark_last_urb_write_with_eot()) return; - const brw_builder bld = brw_builder(&s).at_end(); + const brw_builder bld = brw_builder(&s); /* Emit a URB write to end the thread. On Broadwell, we use this to write * zero to the "TR DS Cache Disable" bit (we haven't implemented a fancy @@ -131,7 +131,7 @@ run_tcs(brw_shader &s) assert(s.stage == MESA_SHADER_TESS_CTRL); struct brw_vue_prog_data *vue_prog_data = brw_vue_prog_data(s.prog_data); - const brw_builder bld = brw_builder(&s).at_end(); + const brw_builder bld = brw_builder(&s); assert(vue_prog_data->dispatch_mode == INTEL_DISPATCH_MODE_TCS_SINGLE_PATCH || vue_prog_data->dispatch_mode == INTEL_DISPATCH_MODE_TCS_MULTI_PATCH); diff --git a/src/intel/compiler/brw_from_nir.cpp b/src/intel/compiler/brw_from_nir.cpp index 234fc0e6e74..b95009e56b5 100644 --- a/src/intel/compiler/brw_from_nir.cpp +++ b/src/intel/compiler/brw_from_nir.cpp @@ -2438,7 +2438,7 @@ brw_shader::gs_urb_per_slot_dword_index(const brw_reg &vertex_count) * Similarly, if the control data header is <= 32 bits, there is only one * DWord, so we can skip channel masks. */ - const brw_builder bld = brw_builder(this).at_end(); + const brw_builder bld = brw_builder(this); const brw_builder abld = bld.annotate("urb per slot offset"); /* Figure out which DWord we're trying to write to using the formula: @@ -2483,7 +2483,7 @@ brw_shader::gs_urb_channel_mask(const brw_reg &dword_index) if (gs.control_data_header_size_bits <= 32) return channel_mask; - const brw_builder bld = brw_builder(this).at_end(); + const brw_builder bld = brw_builder(this); const brw_builder ubld = bld.exec_all(); /* Set the channel masks to 1 << (dword_index % 4), so that we'll @@ -2502,7 +2502,7 @@ brw_shader::emit_gs_control_data_bits(const brw_reg &vertex_count) const struct brw_gs_prog_data *gs_prog_data = brw_gs_prog_data(prog_data); - const brw_builder bld = brw_builder(this).at_end(); + const brw_builder bld = brw_builder(this); const brw_builder abld = bld.annotate("emit control data bits"); brw_reg dword_index = gs_urb_per_slot_dword_index(vertex_count); @@ -7833,7 +7833,7 @@ brw_from_nir(brw_shader *s) .nir = s->nir, .devinfo = s->devinfo, .mem_ctx = ralloc_context(NULL), - .bld = brw_builder(s).at_end(), + .bld = brw_builder(s), }; if (INTEL_DEBUG(DEBUG_ANNOTATION)) diff --git a/src/intel/compiler/brw_lower_simd_width.cpp b/src/intel/compiler/brw_lower_simd_width.cpp index f5306699765..2fbd02d767f 100644 --- a/src/intel/compiler/brw_lower_simd_width.cpp +++ b/src/intel/compiler/brw_lower_simd_width.cpp @@ -658,7 +658,7 @@ brw_lower_simd_width(brw_shader &s) assert(lower_width < inst->exec_size); /* Builder matching the original instruction. */ - const brw_builder bld = brw_builder(&s).at_end(); + const brw_builder bld = brw_builder(&s); const brw_builder ibld = bld.at(block, inst).exec_all(inst->force_writemask_all) .group(inst->exec_size, inst->group / inst->exec_size); diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp index 07347fbe16e..d4c2fe3a7b3 100644 --- a/src/intel/compiler/brw_shader.cpp +++ b/src/intel/compiler/brw_shader.cpp @@ -65,7 +65,7 @@ brw_shader::emit_urb_writes(const brw_reg &gs_vertex_count) unreachable("invalid stage"); } - const brw_builder bld = brw_builder(this).at_end(); + const brw_builder bld = brw_builder(this); brw_reg per_slot_offsets; @@ -330,7 +330,7 @@ brw_shader::emit_urb_writes(const brw_reg &gs_vertex_count) void brw_shader::emit_cs_terminate() { - const brw_builder ubld = brw_builder(this).at_end().exec_all(); + const brw_builder ubld = brw_builder(this).exec_all(); /* We can't directly send from g0, since sends with EOT have to use * g112-127. So, copy it to a virtual register, The register allocator will diff --git a/src/intel/compiler/brw_thread_payload.cpp b/src/intel/compiler/brw_thread_payload.cpp index 4ef7d47eb16..1ddb5316bf9 100644 --- a/src/intel/compiler/brw_thread_payload.cpp +++ b/src/intel/compiler/brw_thread_payload.cpp @@ -102,7 +102,7 @@ brw_gs_thread_payload::brw_gs_thread_payload(brw_shader &v) { struct brw_vue_prog_data *vue_prog_data = brw_vue_prog_data(v.prog_data); struct brw_gs_prog_data *gs_prog_data = brw_gs_prog_data(v.prog_data); - const brw_builder bld = brw_builder(&v).at_end(); + const brw_builder bld = brw_builder(&v); /* R0: thread header. */ unsigned r = reg_unit(v.devinfo); @@ -433,7 +433,7 @@ brw_task_mesh_thread_payload::brw_task_mesh_thread_payload(brw_shader &v) * the address to descriptors. */ - const brw_builder bld = brw_builder(&v).at_end(); + const brw_builder bld = brw_builder(&v); unsigned r = 0; assert(subgroup_id_.file != BAD_FILE); diff --git a/src/intel/compiler/test_lower_scoreboard.cpp b/src/intel/compiler/test_lower_scoreboard.cpp index 48fdb70e185..b47b9ff0ccb 100644 --- a/src/intel/compiler/test_lower_scoreboard.cpp +++ b/src/intel/compiler/test_lower_scoreboard.cpp @@ -62,7 +62,7 @@ scoreboard_test::scoreboard_test() v = new brw_shader(compiler, ¶ms, NULL, &prog_data->base, shader, 8, false, false); - bld = brw_builder(v).at_end(); + bld = brw_builder(v); } scoreboard_test::~scoreboard_test() diff --git a/src/intel/compiler/test_opt_cmod_propagation.cpp b/src/intel/compiler/test_opt_cmod_propagation.cpp index d4e4edc4dc7..ba6c43fd878 100644 --- a/src/intel/compiler/test_opt_cmod_propagation.cpp +++ b/src/intel/compiler/test_opt_cmod_propagation.cpp @@ -69,7 +69,7 @@ cmod_propagation_test::cmod_propagation_test() v = new brw_shader(compiler, ¶ms, NULL, &prog_data->base, shader, 8, false, false); - bld = brw_builder(v).at_end(); + bld = brw_builder(v); devinfo->ver = 9; devinfo->verx10 = devinfo->ver * 10; diff --git a/src/intel/compiler/test_opt_combine_constants.cpp b/src/intel/compiler/test_opt_combine_constants.cpp index 7a6e065a143..ee84bc10b8b 100644 --- a/src/intel/compiler/test_opt_combine_constants.cpp +++ b/src/intel/compiler/test_opt_combine_constants.cpp @@ -65,15 +65,9 @@ struct FSCombineConstantsTest : public ::testing::Test { } }; -static brw_builder -make_builder(brw_shader *s) -{ - return brw_builder(s).at_end(); -} - TEST_F(FSCombineConstantsTest, Simple) { - brw_builder bld = make_builder(shader); + brw_builder bld = brw_builder(shader); brw_reg r = brw_vec8_grf(1, 0); brw_reg imm_a = brw_imm_ud(1); @@ -98,7 +92,7 @@ TEST_F(FSCombineConstantsTest, Simple) TEST_F(FSCombineConstantsTest, DoContainingDo) { - brw_builder bld = make_builder(shader); + brw_builder bld = brw_builder(shader); brw_reg r1 = brw_vec8_grf(1, 0); brw_reg r2 = brw_vec8_grf(2, 0); diff --git a/src/intel/compiler/test_opt_copy_propagation.cpp b/src/intel/compiler/test_opt_copy_propagation.cpp index 430b67aa64d..f2ad005f7e6 100644 --- a/src/intel/compiler/test_opt_copy_propagation.cpp +++ b/src/intel/compiler/test_opt_copy_propagation.cpp @@ -58,7 +58,7 @@ copy_propagation_test::copy_propagation_test() v = new brw_shader(compiler, ¶ms, NULL, &prog_data->base, shader, 8, false, false); - bld = brw_builder(v).at_end(); + bld = brw_builder(v); devinfo->ver = 9; devinfo->verx10 = devinfo->ver * 10; diff --git a/src/intel/compiler/test_opt_cse.cpp b/src/intel/compiler/test_opt_cse.cpp index edf117662dc..cba8b45e979 100644 --- a/src/intel/compiler/test_opt_cse.cpp +++ b/src/intel/compiler/test_opt_cse.cpp @@ -40,7 +40,7 @@ cse_test::cse_test() v = new brw_shader(compiler, ¶ms, NULL, &prog_data->base, shader, 16, false, false); - bld = brw_builder(v).at_end(); + bld = brw_builder(v); devinfo->verx10 = 125; devinfo->ver = devinfo->verx10 / 10; diff --git a/src/intel/compiler/test_opt_saturate_propagation.cpp b/src/intel/compiler/test_opt_saturate_propagation.cpp index 34e940015cd..003cf0d1e88 100644 --- a/src/intel/compiler/test_opt_saturate_propagation.cpp +++ b/src/intel/compiler/test_opt_saturate_propagation.cpp @@ -58,7 +58,7 @@ saturate_propagation_test::saturate_propagation_test() v = new brw_shader(compiler, ¶ms, NULL, &prog_data->base, shader, 16, false, false); - bld = brw_builder(v).at_end(); + bld = brw_builder(v); devinfo->ver = 9; devinfo->verx10 = devinfo->ver * 10;