From 8e188f8f2e95c39c0c9252f539cb43fc163c732d Mon Sep 17 00:00:00 2001 From: Connor Abbott Date: Wed, 8 Sep 2021 15:05:20 +0200 Subject: [PATCH] freedreno/a6xx: Fix VS primid with tess + GS. Analogous to the previous commit. Fixes: 8115cde3ba6 ("tu, freedreno/a6xx, ir3: Rewrite tess PrimID handling") Part-of: --- src/gallium/drivers/freedreno/a6xx/fd6_program.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_program.c b/src/gallium/drivers/freedreno/a6xx/fd6_program.c index 20fe9699dc2..13e8d1d3b2b 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_program.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_program.c @@ -364,10 +364,10 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx, layer_regid = ir3_find_output_regid(vs, VARYING_SLOT_LAYER); vertex_regid = ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID); instance_regid = ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID); - if (gs) - vs_primitive_regid = ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID); - else if (hs) + if (hs) vs_primitive_regid = ir3_find_sysval_regid(hs, SYSTEM_VALUE_PRIMITIVE_ID); + else if (gs) + vs_primitive_regid = ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID); else vs_primitive_regid = regid(63, 0);