From 8d3e76c25061bcece020967a25a102513e384a15 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Thu, 24 Jul 2025 14:10:09 -0400 Subject: [PATCH] nir: split nir_move_load_frag_coord from nir_move_load_input It's a pure system value on AMD, not an input. Reviewed-by: Alyssa Rosenzweig Part-of: --- src/amd/vulkan/radv_pipeline.c | 7 ++++--- src/asahi/compiler/agx_compile.c | 12 ++++++------ src/compiler/nir/nir.h | 1 + src/compiler/nir/nir_opt_sink.c | 15 +++++++++------ src/gallium/auxiliary/nir/nir_to_tgsi.c | 2 +- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 2 +- src/gallium/drivers/r300/compiler/nir_to_rc.c | 2 +- src/imagination/rogue/rogue_nir.c | 3 ++- src/panfrost/compiler/bifrost_compile.c | 5 +++-- src/panfrost/midgard/midgard_compile.c | 5 +++-- 10 files changed, 31 insertions(+), 23 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 7dc1c107ced..2a3522f0c27 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -477,10 +477,10 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_graphics_stat NIR_PASS(_, stage->nir, nir_opt_move, sink_opts); } else { if (stage->stage != MESA_SHADER_FRAGMENT || !pdev->cache_key.disable_sinking_load_input_fs) - sink_opts |= nir_move_load_input; + sink_opts |= nir_move_load_input | nir_move_load_frag_coord; NIR_PASS(_, stage->nir, nir_opt_sink, sink_opts); - NIR_PASS(_, stage->nir, nir_opt_move, sink_opts | nir_move_load_input); + NIR_PASS(_, stage->nir, nir_opt_move, sink_opts | nir_move_load_input | nir_move_load_frag_coord); } } @@ -691,7 +691,8 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_graphics_stat NIR_PASS(_, stage->nir, nir_opt_sink, sink_opts); nir_move_options move_opts = nir_move_const_undef | nir_move_load_ubo | nir_move_load_input | - nir_move_comparisons | nir_move_copies | nir_dont_move_byte_word_vecs | nir_move_alu; + nir_move_load_frag_coord | nir_move_comparisons | nir_move_copies | + nir_dont_move_byte_word_vecs | nir_move_alu; NIR_PASS(_, stage->nir, nir_opt_move, move_opts); /* Run nir_opt_move again to make sure that comparision are as close as possible to the first use to prevent SCC diff --git a/src/asahi/compiler/agx_compile.c b/src/asahi/compiler/agx_compile.c index b3082728807..f66d5fc4a73 100644 --- a/src/asahi/compiler/agx_compile.c +++ b/src/asahi/compiler/agx_compile.c @@ -3273,9 +3273,9 @@ agx_optimize_nir(nir_shader *nir, bool soft_fault, uint16_t *preamble_size, /* Cleanup optimizations */ nir_move_options move_all = nir_move_const_undef | nir_move_load_ubo | - nir_move_load_input | nir_move_comparisons | - nir_move_copies | nir_move_load_ssbo | - nir_move_alu; + nir_move_load_input | nir_move_load_frag_coord | + nir_move_comparisons | nir_move_copies | + nir_move_load_ssbo | nir_move_alu; NIR_PASS(_, nir, nir_opt_sink, move_all); NIR_PASS(_, nir, nir_opt_move, move_all); @@ -3890,9 +3890,9 @@ agx_preprocess_nir(nir_shader *nir) /* Move before lowering */ nir_move_options move_all = nir_move_const_undef | nir_move_load_ubo | - nir_move_load_input | nir_move_comparisons | - nir_move_copies | nir_move_load_ssbo | - nir_move_alu; + nir_move_load_input | nir_move_load_frag_coord | + nir_move_comparisons | nir_move_copies | + nir_move_load_ssbo | nir_move_alu; NIR_PASS(_, nir, nir_opt_sink, move_all); NIR_PASS(_, nir, nir_opt_move, move_all); diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index 419a6964034..fb860d1bb7e 100644 --- a/src/compiler/nir/nir.h +++ b/src/compiler/nir/nir.h @@ -6203,6 +6203,7 @@ typedef enum { nir_move_load_ubo = BITFIELD_BIT(6), nir_move_load_ssbo = BITFIELD_BIT(7), nir_move_load_uniform = BITFIELD_BIT(8), + nir_move_load_frag_coord = BITFIELD_BIT(9), } nir_move_options; bool nir_can_move_instr(nir_instr *instr, nir_move_options options); diff --git a/src/compiler/nir/nir_opt_sink.c b/src/compiler/nir/nir_opt_sink.c index 6a9c4ea91e4..8c1efdee649 100644 --- a/src/compiler/nir/nir_opt_sink.c +++ b/src/compiler/nir/nir_opt_sink.c @@ -117,6 +117,14 @@ can_sink_instr(nir_instr *instr, nir_move_options options, bool *can_mov_out_of_ *can_mov_out_of_loop = false; switch (intrin->intrinsic) { + case nir_intrinsic_load_input: + case nir_intrinsic_load_interpolated_input: + case nir_intrinsic_load_per_vertex_input: + case nir_intrinsic_load_per_primitive_input: + case nir_intrinsic_load_attribute_pan: + *can_mov_out_of_loop = true; + return options & nir_move_load_input; + case nir_intrinsic_load_ubo: case nir_intrinsic_load_ubo_vec4: case nir_intrinsic_load_global_constant_offset: @@ -133,18 +141,13 @@ can_sink_instr(nir_instr *instr, nir_move_options options, bool *can_mov_out_of_ intrin->intrinsic == nir_intrinsic_load_global_bounded; return options & nir_move_load_ssbo; - case nir_intrinsic_load_input: - case nir_intrinsic_load_per_primitive_input: - case nir_intrinsic_load_interpolated_input: - case nir_intrinsic_load_per_vertex_input: case nir_intrinsic_load_frag_coord: case nir_intrinsic_load_frag_coord_z: case nir_intrinsic_load_frag_coord_w: case nir_intrinsic_load_frag_coord_zw_pan: case nir_intrinsic_load_pixel_coord: - case nir_intrinsic_load_attribute_pan: *can_mov_out_of_loop = true; - return options & nir_move_load_input; + return options & nir_move_load_frag_coord; case nir_intrinsic_load_uniform: case nir_intrinsic_load_kernel_input: diff --git a/src/gallium/auxiliary/nir/nir_to_tgsi.c b/src/gallium/auxiliary/nir/nir_to_tgsi.c index dc31a256c3b..0629511a319 100644 --- a/src/gallium/auxiliary/nir/nir_to_tgsi.c +++ b/src/gallium/auxiliary/nir/nir_to_tgsi.c @@ -3982,7 +3982,7 @@ const void *nir_to_tgsi_options(struct nir_shader *s, } nir_move_options move_all = - nir_move_const_undef | nir_move_load_ubo | nir_move_load_input | + nir_move_const_undef | nir_move_load_ubo | nir_move_load_input | nir_move_load_frag_coord | nir_move_comparisons | nir_move_copies | nir_move_load_ssbo; NIR_PASS(_, s, nir_opt_move, move_all); diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp index ae9e1c756e9..bdc18527213 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp @@ -3495,7 +3495,7 @@ Converter::run() (nir_move_options)(nir_move_const_undef | nir_move_load_ubo | nir_move_load_uniform | - nir_move_load_input); + nir_move_load_input | nir_move_load_frag_coord); NIR_PASS(_, nir, nir_opt_sink, move_options); NIR_PASS(_, nir, nir_opt_move, move_options); diff --git a/src/gallium/drivers/r300/compiler/nir_to_rc.c b/src/gallium/drivers/r300/compiler/nir_to_rc.c index 1a8e6bd2237..e93074bddf7 100644 --- a/src/gallium/drivers/r300/compiler/nir_to_rc.c +++ b/src/gallium/drivers/r300/compiler/nir_to_rc.c @@ -2088,7 +2088,7 @@ nir_to_rc(struct nir_shader *s, struct pipe_screen *screen, NIR_PASS(_, s, nir_opt_shrink_vectors, false); NIR_PASS(_, s, nir_opt_dce); - nir_move_options move_all = nir_move_const_undef | nir_move_load_ubo | nir_move_load_input | + nir_move_options move_all = nir_move_const_undef | nir_move_load_ubo | nir_move_load_input | nir_move_load_frag_coord | nir_move_comparisons | nir_move_copies | nir_move_load_ssbo; NIR_PASS(_, s, nir_opt_move, move_all); diff --git a/src/imagination/rogue/rogue_nir.c b/src/imagination/rogue/rogue_nir.c index cd0c8cd8374..256c7416af8 100644 --- a/src/imagination/rogue/rogue_nir.c +++ b/src/imagination/rogue/rogue_nir.c @@ -150,7 +150,8 @@ static void rogue_nir_passes(struct rogue_build_ctx *ctx, /* Disabled for now since we want to try and keep them vectorised and group * them. */ /* TODO: Investigate this further. */ - /* NIR_PASS(_, nir, nir_opt_move, nir_move_load_ubo | nir_move_load_input); + /* NIR_PASS(_, nir, nir_opt_move, nir_move_load_ubo | nir_move_load_input | + * nir_move_load_frag_coord); */ /* TODO: Re-enable scheduling after register pressure tweaks. */ diff --git a/src/panfrost/compiler/bifrost_compile.c b/src/panfrost/compiler/bifrost_compile.c index 873be4127de..bc76b7adcc8 100644 --- a/src/panfrost/compiler/bifrost_compile.c +++ b/src/panfrost/compiler/bifrost_compile.c @@ -5541,8 +5541,9 @@ bi_optimize_nir(nir_shader *nir, unsigned gpu_id, nir_variable_mode robust2_mode /* Backend scheduler is purely local, so do some global optimizations * to reduce register pressure. */ nir_move_options move_all = nir_move_const_undef | nir_move_load_ubo | - nir_move_load_input | nir_move_comparisons | - nir_move_copies | nir_move_load_ssbo; + nir_move_load_input | nir_move_load_frag_coord | + nir_move_comparisons | nir_move_copies | + nir_move_load_ssbo; NIR_PASS(_, nir, nir_opt_sink, move_all); NIR_PASS(_, nir, nir_opt_move, move_all); diff --git a/src/panfrost/midgard/midgard_compile.c b/src/panfrost/midgard/midgard_compile.c index 11ac910c0d3..c2f76cf26d2 100644 --- a/src/panfrost/midgard/midgard_compile.c +++ b/src/panfrost/midgard/midgard_compile.c @@ -545,8 +545,9 @@ optimise_nir(nir_shader *nir, unsigned quirks, bool is_blend) /* Backend scheduler is purely local, so do some global optimizations * to reduce register pressure. */ nir_move_options move_all = nir_move_const_undef | nir_move_load_ubo | - nir_move_load_input | nir_move_comparisons | - nir_move_copies | nir_move_load_ssbo; + nir_move_load_input | nir_move_load_frag_coord | + nir_move_comparisons | nir_move_copies | + nir_move_load_ssbo; NIR_PASS(_, nir, nir_opt_sink, move_all); NIR_PASS(_, nir, nir_opt_move, move_all);