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965: missing code from last commit

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This commit is contained in:
Keith Whitwell
2007-12-13 15:39:34 +00:00
parent 559750298a
commit 8cd608d5ba
5 changed files with 11 additions and 17 deletions
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src/mesa/pipe/i965simple/brw_context.h
+1 -1
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@@ -489,7 +489,7 @@ struct brw_context
/* Arrays with buffer objects to copy non-bufferobj arrays into
* for upload:
*/
struct pipe_vertex_buffer vbo_array[PIPE_ATTRIB_MAX];
struct pipe_vertex_buffer *vbo_array[PIPE_ATTRIB_MAX];
struct brw_vertex_element inputs[PIPE_ATTRIB_MAX];
src/mesa/pipe/i965simple/brw_draw.c
-1
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@@ -151,7 +151,6 @@ static boolean brw_try_draw_elements( struct pipe_context *pipe,
unsigned count )
{
struct brw_context *brw = brw_context(pipe);
boolean retval = FALSE;
/* Set the first primitive ahead of validate_state:
*/
src/mesa/pipe/i965simple/brw_draw_upload.c
+6 -6
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@@ -217,18 +217,18 @@ boolean brw_upload_vertex_buffers( struct brw_context *brw )
for (i = 0; i < BRW_VEP_MAX; i++)
{
if (brw->vb.vbo_array[i] == NULL) {
if (brw->vb.vbo_array[i]->buffer == NULL) {
nr_enabled = i;
break;
}
vbp.vb[i].vb0.bits.pitch = brw->vb.vbo_array[i].pitch;
vbp.vb[i].vb0.bits.pitch = brw->vb.vbo_array[i]->pitch;
vbp.vb[i].vb0.bits.pad = 0;
vbp.vb[i].vb0.bits.access_type = BRW_VERTEXBUFFER_ACCESS_VERTEXDATA;
vbp.vb[i].vb0.bits.vb_index = i;
vbp.vb[i].offset = brw->vb.vbo_array[i].buffer_offset;
vbp.vb[i].buffer = brw->vb.vbo_array[i].buffer;
vbp.vb[i].max_index = brw->vb.vbo_array[i].max_index;
vbp.vb[i].offset = brw->vb.vbo_array[i]->buffer_offset;
vbp.vb[i].buffer = brw->vb.vbo_array[i]->buffer;
vbp.vb[i].max_index = brw->vb.vbo_array[i]->max_index;
}
@@ -263,7 +263,7 @@ boolean brw_upload_vertex_elements( struct brw_context *brw )
for (i = 0; i < nr_enabled; i++) {
struct brw_vertex_element *input = &brw->vb.inputs[i];
switch (brw->vb.vbo_array[input->vep.ve0.vertex_buffer_index].pitch) {
switch (brw->vb.vbo_array[input->vep.ve0.vertex_buffer_index]->pitch) {
case 0: input->vep.ve1.vfcomponent0 = BRW_VFCOMPONENT_STORE_0;
case 1: input->vep.ve1.vfcomponent1 = BRW_VFCOMPONENT_STORE_0;
case 2: input->vep.ve1.vfcomponent2 = BRW_VFCOMPONENT_STORE_0;
src/mesa/pipe/i965simple/brw_misc_state.c
+1 -3
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@@ -202,9 +202,7 @@ static void upload_depthbuffer(struct brw_context *brw)
OUT_BATCH(((depth_surface->pitch * depth_surface->cpp) - 1) |
(format << 18) |
(BRW_TILEWALK_YMAJOR << 26) |
#if 0
(depth_surface->region->tiled << 27) |
#endif
// (depth_surface->region->tiled << 27) |
(BRW_SURFACE_2D << 29));
OUT_RELOC(depth_surface->buffer,
PIPE_BUFFER_FLAG_READ | PIPE_BUFFER_FLAG_WRITE, 0);
src/mesa/pipe/i965simple/brw_state.c
+3 -6
View File
@@ -273,14 +273,11 @@ static void brw_set_viewport_state( struct pipe_context *pipe,
static void brw_set_vertex_buffer( struct pipe_context *pipe,
unsigned index,
const struct pipe_vertex_buffer *buffer )
unsigned index,
const struct pipe_vertex_buffer *buffer )
{
struct brw_context *brw = brw_context(pipe);
brw->vb.vbo_array[index] = *buffer;
if (index > brw->vb.last_vb)
brw->vb.last_vb = index;
assert(brw->vb.last_vb < BRW_VEP_MAX);
brw->vb.vbo_array[index] = buffer;
}
static void brw_set_vertex_element(struct pipe_context *pipe,