diff --git a/src/intel/genxml/gen12.xml b/src/intel/genxml/gen12.xml
index 0bf9fcb157a..541a6a6ba56 100644
--- a/src/intel/genxml/gen12.xml
+++ b/src/intel/genxml/gen12.xml
@@ -1324,6 +1324,7 @@
     <field name="Protected Memory Disable" start="59" end="59" type="bool" />
     <field name="Tile Cache Flush Enable" start="60" end="60" type="bool" />
     <field name="Command Cache Invalidate Enable" start="61" end="61" type="bool" />
+    <field name="L3 Fabric Flush" start="62" end="62" type="bool" />
     <field name="Address" start="66" end="111" type="address" />
     <field name="Immediate Data" start="128" end="191" type="uint" />
   </instruction>
diff --git a/src/intel/genxml/gen125.xml b/src/intel/genxml/gen125.xml
index 484ba17e1cc..a33876bfee4 100644
--- a/src/intel/genxml/gen125.xml
+++ b/src/intel/genxml/gen125.xml
@@ -1826,6 +1826,7 @@
     <field name="Protected Memory Disable" start="59" end="59" type="bool" />
     <field name="Tile Cache Flush Enable" start="60" end="60" type="bool" />
     <field name="Command Cache Invalidate Enable" start="61" end="61" type="bool" />
+    <field name="L3 Fabric Flush" start="62" end="62" type="bool" />
     <field name="TBIMR Force Batch Closure" start="63" end="63" type="uint">
       <value name="No Batch Closure" value="0" />
       <value name="Close Batch" value="1" />