From 8be506039da40e1d6b57a6146d3843a74ced4b68 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Wed, 9 Nov 2022 20:17:42 -0500 Subject: [PATCH] asahi: Note some magic bits used with memoryless RTs Obviously there can't *actually* be memoryless render targets, because how would partial renders work? The control stream with memoryless looks like everything would if it went to memory (e.g. full 2D MSAA attachments for the partial loads/stores even if only a resolved 2D image for the final store). Except the memoryless attachments all load from the same address 0xeeee0000. Clearly that's not actually what happens, so what gives? Unclear... but I see the magic bits mentioned here set, and I assume there are some firmware (or kernel) shenanigans used to JIT allocate the backing storage for partial renders. Signed-off-by: Alyssa Rosenzweig Part-of: --- src/asahi/lib/cmdbuf.xml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/asahi/lib/cmdbuf.xml b/src/asahi/lib/cmdbuf.xml index 45f7e60e9ed..ef82ed15c69 100644 --- a/src/asahi/lib/cmdbuf.xml +++ b/src/asahi/lib/cmdbuf.xml @@ -830,6 +830,7 @@ + @@ -890,6 +891,7 @@ +