diff --git a/src/amd/common/ac_nir_lower_esgs_io_to_mem.c b/src/amd/common/ac_nir_lower_esgs_io_to_mem.c index badeb07db16..c1d58029bab 100644 --- a/src/amd/common/ac_nir_lower_esgs_io_to_mem.c +++ b/src/amd/common/ac_nir_lower_esgs_io_to_mem.c @@ -222,8 +222,8 @@ gs_per_vertex_input_vertex_offset_gfx9(nir_builder *b, lower_esgs_io_state *st, { if (nir_src_is_const(*vertex_src)) { unsigned vertex = nir_src_as_uint(*vertex_src); - return nir_ubfe(b, gs_get_vertex_offset(b, st, vertex / 2u), - nir_imm_int(b, (vertex & 1u) * 16u), nir_imm_int(b, 16u)); + return nir_ubfe_imm(b, gs_get_vertex_offset(b, st, vertex / 2u), + (vertex & 1u) * 16u, 16u); } nir_ssa_def *vertex_offset = gs_get_vertex_offset(b, st, 0); diff --git a/src/amd/common/ac_nir_lower_ngg.c b/src/amd/common/ac_nir_lower_ngg.c index fa29bde51e0..9ce9f7bf3bf 100644 --- a/src/amd/common/ac_nir_lower_ngg.c +++ b/src/amd/common/ac_nir_lower_ngg.c @@ -412,14 +412,14 @@ emit_pack_ngg_prim_exp_arg(nir_builder *b, unsigned num_vertices_per_primitives, for (unsigned i = 0; i < num_vertices_per_primitives; ++i) { assert(vertex_indices[i]); - arg = nir_ior(b, arg, nir_ishl(b, vertex_indices[i], nir_imm_int(b, 10u * i))); + arg = nir_ior(b, arg, nir_ishl_imm(b, vertex_indices[i], 10u * i)); } if (is_null_prim) { if (is_null_prim->bit_size == 1) is_null_prim = nir_b2i32(b, is_null_prim); assert(is_null_prim->bit_size == 32); - arg = nir_ior(b, arg, nir_ishl(b, is_null_prim, nir_imm_int(b, 31u))); + arg = nir_ior(b, arg, nir_ishl_imm(b, is_null_prim, 31u)); } return arg; @@ -493,10 +493,10 @@ ngg_nogs_init_vertex_indices_vars(nir_builder *b, nir_function_impl *impl, lower s->gs_vtx_indices_vars[v] = nir_local_variable_create(impl, glsl_uint_type(), "gs_vtx_addr"); nir_ssa_def *vtx = s->options->passthrough ? - nir_ubfe(b, nir_load_packed_passthrough_primitive_amd(b), - nir_imm_int(b, 10 * v), nir_imm_int(b, 9)) : - nir_ubfe(b, nir_load_gs_vertex_offset_amd(b, .base = v / 2u), - nir_imm_int(b, (v & 1u) * 16u), nir_imm_int(b, 16u)); + nir_ubfe_imm(b, nir_load_packed_passthrough_primitive_amd(b), + 10 * v, 9) : + nir_ubfe_imm(b, nir_load_gs_vertex_offset_amd(b, .base = v / 2u), + (v & 1u) * 16u, 16u); nir_store_var(b, s->gs_vtx_indices_vars[v], vtx, 0x1); } @@ -542,8 +542,8 @@ nogs_prim_gen_query(nir_builder *b, lower_ngg_nogs_state *s) nir_if *if_elected = nir_push_if(b, nir_elect(b, 1)); { /* Number of input primitives in the current wave. */ - nir_ssa_def *num_input_prims = nir_ubfe(b, nir_load_merged_wave_info_amd(b), - nir_imm_int(b, 8), nir_imm_int(b, 8)); + nir_ssa_def *num_input_prims = nir_ubfe_imm(b, nir_load_merged_wave_info_amd(b), + 8, 8); /* Add to stream 0 primitive generated counter. */ nir_atomic_add_gen_prim_count_amd(b, num_input_prims, .stream_id = 0); @@ -2825,7 +2825,7 @@ lower_ngg_gs_emit_vertex_with_counter(nir_builder *b, nir_intrinsic_instr *intri nir_ssa_def *prim_flag = nir_ior(b, vertex_live_flag, complete_flag); if (s->num_vertices_per_primitive == 3) { nir_ssa_def *odd = nir_iand(b, current_vtx_per_prim, complete_flag); - nir_ssa_def *odd_flag = nir_ishl(b, odd, nir_imm_int(b, 1)); + nir_ssa_def *odd_flag = nir_ishl_imm(b, odd, 1); prim_flag = nir_ior(b, prim_flag, odd_flag); } @@ -2920,7 +2920,7 @@ ngg_gs_export_primitives(nir_builder *b, nir_ssa_def *max_num_out_prims, nir_ssa * make sure the vertex order is so that the front/back is correct, and the provoking vertex is kept. */ - nir_ssa_def *is_odd = nir_ubfe(b, primflag_0, nir_imm_int(b, 1), nir_imm_int(b, 1)); + nir_ssa_def *is_odd = nir_ubfe_imm(b, primflag_0, 1, 1); nir_ssa_def *provoking_vertex_index = nir_load_provoking_vtx_in_prim_amd(b); nir_ssa_def *provoking_vertex_first = nir_ieq_imm(b, provoking_vertex_index, 0); @@ -3092,7 +3092,7 @@ ngg_gs_out_prim_all_vtxptr(nir_builder *b, nir_ssa_def *last_vtxidx, nir_ssa_def bool primitive_is_triangle = s->num_vertices_per_primitive == 3; nir_ssa_def *is_odd = primitive_is_triangle ? - nir_ubfe(b, last_vtx_primflag, nir_imm_int(b, 1), nir_imm_int(b, 1)) : NULL; + nir_ubfe_imm(b, last_vtx_primflag, 1, 1) : NULL; for (unsigned i = 0; i < s->num_vertices_per_primitive - 1; i++) { nir_ssa_def *vtxidx = nir_iadd_imm(b, last_vtxidx, -(last_vtx - i)); diff --git a/src/amd/common/ac_nir_lower_taskmesh_io_to_mem.c b/src/amd/common/ac_nir_lower_taskmesh_io_to_mem.c index 92290732204..56b817128db 100644 --- a/src/amd/common/ac_nir_lower_taskmesh_io_to_mem.c +++ b/src/amd/common/ac_nir_lower_taskmesh_io_to_mem.c @@ -90,7 +90,7 @@ task_draw_ready_bit(nir_builder *b, nir_ssa_def *workgroup_index = task_workgroup_index(b, s); nir_ssa_def *idx = nir_iadd_nuw(b, ring_entry, workgroup_index); - return nir_u2u8(b, nir_ubfe(b, idx, nir_imm_int(b, util_bitcount(s->num_entries - 1)), nir_imm_int(b, 1))); + return nir_u2u8(b, nir_ubfe_imm(b, idx, util_bitcount(s->num_entries - 1), 1)); } static nir_ssa_def * diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index 060ffc76a67..6f5356c773d 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -3346,7 +3346,7 @@ static nir_ssa_def *gfx10_nir_meta_addr_from_coord(nir_builder *b, const struct } } - address = nir_ior(b, address, nir_ishl(b, v, nir_imm_int(b, i))); + address = nir_ior(b, address, nir_ishl_imm(b, v, i)); } unsigned blkMask = (1 << blkSizeLog2) - 1; @@ -3356,15 +3356,14 @@ static nir_ssa_def *gfx10_nir_meta_addr_from_coord(nir_builder *b, const struct nir_ssa_def *yb = nir_ushr_imm(b, y, meta_block_height_log2); nir_ssa_def *pb = nir_ushr_imm(b, meta_pitch, meta_block_width_log2); nir_ssa_def *blkIndex = nir_iadd(b, nir_imul(b, yb, pb), xb); - nir_ssa_def *pipeXor = nir_iand_imm(b, nir_ishl(b, nir_iand_imm(b, pipe_xor, pipeMask), - nir_imm_int(b, m_pipeInterleaveLog2)), blkMask); + nir_ssa_def *pipeXor = nir_iand_imm(b, nir_ishl_imm(b, nir_iand_imm(b, pipe_xor, pipeMask), + m_pipeInterleaveLog2), blkMask); if (bit_position) - *bit_position = nir_ishl(b, nir_iand(b, address, nir_imm_int(b, 1)), - nir_imm_int(b, 2)); + *bit_position = nir_ishl_imm(b, nir_iand_imm(b, address, 1), 2); return nir_iadd(b, nir_iadd(b, nir_imul(b, meta_slice_size, z), - nir_imul(b, blkIndex, nir_ishl(b, one, nir_imm_int(b, blkSizeLog2)))), + nir_imul(b, blkIndex, nir_ishl_imm(b, one, blkSizeLog2))), nir_ixor(b, nir_ushr(b, address, one), pipeXor)); } @@ -3417,23 +3416,22 @@ static nir_ssa_def *gfx9_nir_meta_addr_from_coord(nir_builder *b, const struct r xor = nir_ixor(b, xor, ison); } - address = nir_ior(b, address, nir_ishl(b, xor, nir_imm_int(b, i))); + address = nir_ior(b, address, nir_ishl_imm(b, xor, i)); } /* Fill the remaining bits with the block index. */ unsigned last = num_bits - 1; address = nir_ior(b, address, - nir_ishl(b, nir_ushr_imm(b, blockIndex, + nir_ishl_imm(b, nir_ushr_imm(b, blockIndex, equation->u.gfx9.bit[last].coord[0].ord), - nir_imm_int(b, last))); + last)); if (bit_position) - *bit_position = nir_ishl(b, nir_iand(b, address, nir_imm_int(b, 1)), - nir_imm_int(b, 2)); + *bit_position = nir_ishl_imm(b, nir_iand_imm(b, address, 1), 2); nir_ssa_def *pipeXor = nir_iand_imm(b, pipe_xor, (1 << numPipeBits) - 1); return nir_ixor(b, nir_ushr(b, address, one), - nir_ishl(b, pipeXor, nir_imm_int(b, m_pipeInterleaveLog2))); + nir_ishl_imm(b, pipeXor, m_pipeInterleaveLog2)); } nir_ssa_def *ac_nir_dcc_addr_from_coord(nir_builder *b, const struct radeon_info *info, diff --git a/src/amd/vulkan/nir/radv_nir_lower_abi.c b/src/amd/vulkan/nir/radv_nir_lower_abi.c index 95e2076aaed..8b22edd890f 100644 --- a/src/amd/vulkan/nir/radv_nir_lower_abi.c +++ b/src/amd/vulkan/nir/radv_nir_lower_abi.c @@ -140,8 +140,8 @@ lower_abi_instr(nir_builder *b, nir_instr *instr, void *state) case nir_intrinsic_load_ring_attr_offset_amd: { nir_ssa_def *ring_attr_offset = ac_nir_load_arg(b, &s->args->ac, s->args->ac.gs_attr_offset); replacement = - nir_ishl(b, nir_ubfe(b, ring_attr_offset, nir_imm_int(b, 0), nir_imm_int(b, 15)), - nir_imm_int(b, 9)); /* 512b increments. */ + nir_ishl_imm(b, nir_ubfe_imm(b, ring_attr_offset, 0, 15), + 9); /* 512b increments. */ break; } @@ -181,12 +181,12 @@ lower_abi_instr(nir_builder *b, nir_instr *instr, void *state) ac_nir_load_arg(b, &s->args->ac, s->args->ac.gs_vtx_offset[nir_intrinsic_base(intrin)]); break; case nir_intrinsic_load_workgroup_num_input_vertices_amd: - replacement = nir_ubfe(b, ac_nir_load_arg(b, &s->args->ac, s->args->ac.gs_tg_info), - nir_imm_int(b, 12), nir_imm_int(b, 9)); + replacement = nir_ubfe_imm(b, ac_nir_load_arg(b, &s->args->ac, s->args->ac.gs_tg_info), + 12, 9); break; case nir_intrinsic_load_workgroup_num_input_primitives_amd: - replacement = nir_ubfe(b, ac_nir_load_arg(b, &s->args->ac, s->args->ac.gs_tg_info), - nir_imm_int(b, 22), nir_imm_int(b, 9)); + replacement = nir_ubfe_imm(b, ac_nir_load_arg(b, &s->args->ac, s->args->ac.gs_tg_info), + 22, 9); break; case nir_intrinsic_load_packed_passthrough_primitive_amd: /* NGG passthrough mode: the HW already packs the primitive export value to a single register. diff --git a/src/compiler/nir/nir_lower_fp16_conv.c b/src/compiler/nir/nir_lower_fp16_conv.c index 539264d3a24..ea6500c89a9 100644 --- a/src/compiler/nir/nir_lower_fp16_conv.c +++ b/src/compiler/nir/nir_lower_fp16_conv.c @@ -53,11 +53,11 @@ half_rounded(nir_builder *b, nir_ssa_def *value, nir_ssa_def *guard, nir_ssa_def case nir_rounding_mode_rtne: return nir_iadd(b, value, nir_iand(b, guard, nir_ior(b, sticky, value))); case nir_rounding_mode_ru: - sign = nir_ushr(b, sign, nir_imm_int(b, 31)); + sign = nir_ushr_imm(b, sign, 31); return nir_iadd(b, value, nir_iand(b, nir_inot(b, sign), nir_ior(b, guard, sticky))); case nir_rounding_mode_rd: - sign = nir_ushr(b, sign, nir_imm_int(b, 31)); + sign = nir_ushr_imm(b, sign, 31); return nir_iadd(b, value, nir_iand(b, sign, nir_ior(b, guard, sticky))); default: @@ -73,10 +73,10 @@ float_to_half_impl(nir_builder *b, nir_ssa_def *src, nir_rounding_mode mode) if (src->bit_size == 64) src = nir_f2f32(b, src); - nir_ssa_def *sign = nir_iand(b, src, nir_imm_int(b, 0x80000000)); + nir_ssa_def *sign = nir_iand_imm(b, src, 0x80000000); nir_ssa_def *one = nir_imm_int(b, 1); - nir_ssa_def *abs = nir_iand(b, src, nir_imm_int(b, 0x7FFFFFFF)); + nir_ssa_def *abs = nir_iand_imm(b, src, 0x7FFFFFFF); /* NaN or INF. For rtne, overflow also becomes INF, so combine the comparisons */ nir_push_if(b, nir_ige(b, abs, mode == nir_rounding_mode_rtne ? f16max : f32infinity)); nir_ssa_def *inf_nanfp16 = nir_bcsel(b, @@ -112,22 +112,22 @@ float_to_half_impl(nir_builder *b, nir_ssa_def *src, nir_rounding_mode mode) /* FP16 will be normal */ nir_ssa_def *value = nir_ior(b, - nir_ishl(b, - nir_isub(b, - nir_ushr(b, abs, nir_imm_int(b, 23)), - nir_imm_int(b, 112)), - nir_imm_int(b, 10)), - nir_iand(b, nir_ushr(b, abs, nir_imm_int(b, 13)), nir_imm_int(b, 0x3FFF))); - nir_ssa_def *guard = nir_iand(b, nir_ushr(b, abs, nir_imm_int(b, 12)), one); - nir_ssa_def *sticky = nir_bcsel(b, nir_ine(b, nir_iand(b, abs, nir_imm_int(b, 0xFFF)), zero), one, zero); + nir_ishl_imm(b, + nir_isub(b, + nir_ushr_imm(b, abs, 23), + nir_imm_int(b, 112)), + 10), + nir_iand_imm(b, nir_ushr_imm(b, abs, 13), 0x3FFF)); + nir_ssa_def *guard = nir_iand(b, nir_ushr_imm(b, abs, 12), one); + nir_ssa_def *sticky = nir_bcsel(b, nir_ine(b, nir_iand_imm(b, abs, 0xFFF), zero), one, zero); nir_ssa_def *normal_fp16 = half_rounded(b, value, guard, sticky, sign, mode); nir_push_else(b, NULL); nir_push_if(b, nir_ige_imm(b, abs, 102 << 23)); /* FP16 will be denormal */ - nir_ssa_def *i = nir_isub(b, nir_imm_int(b, 125), nir_ushr(b, abs, nir_imm_int(b, 23))); - nir_ssa_def *masked = nir_ior(b, nir_iand(b, abs, nir_imm_int(b, 0x7FFFFF)), nir_imm_int(b, 0x800000)); + nir_ssa_def *i = nir_isub_imm(b, 125, nir_ushr_imm(b, abs, 23)); + nir_ssa_def *masked = nir_ior_imm(b, nir_iand_imm(b, abs, 0x7FFFFF), 0x800000); value = nir_ushr(b, masked, nir_iadd(b, i, one)); guard = nir_iand(b, nir_ushr(b, masked, i), one); sticky = nir_bcsel(b, nir_ine(b, nir_iand(b, masked, nir_isub(b, nir_ishl(b, one, i), one)), zero), one, zero); @@ -166,7 +166,7 @@ float_to_half_impl(nir_builder *b, nir_ssa_def *src, nir_rounding_mode mode) nir_pop_if(b, NULL); nir_ssa_def *fp16 = nir_if_phi(b, inf_nanfp16, finite_or_overflowed_fp16); - return nir_u2u16(b, nir_ior(b, fp16, nir_ushr(b, sign, nir_imm_int(b, 16)))); + return nir_u2u16(b, nir_ior(b, fp16, nir_ushr_imm(b, sign, 16))); } static bool diff --git a/src/compiler/nir/nir_lower_int64.c b/src/compiler/nir/nir_lower_int64.c index 6b64dd65f1f..42976da34ec 100644 --- a/src/compiler/nir/nir_lower_int64.c +++ b/src/compiler/nir/nir_lower_int64.c @@ -240,7 +240,7 @@ lower_ishr64(nir_builder *b, nir_ssa_def *x, nir_ssa_def *y) hi_shifted); nir_ssa_def *res_if_ge_32 = nir_pack_64_2x32_split(b, nir_ishr(b, x_hi, reverse_count), - nir_ishr(b, x_hi, nir_imm_int(b, 31))); + nir_ishr_imm(b, x_hi, 31)); return nir_bcsel(b, nir_ieq_imm(b, y, 0), x, nir_bcsel(b, nir_uge_imm(b, y, 32), @@ -1259,8 +1259,8 @@ lower_scan_iadd64(nir_builder *b, const nir_intrinsic_instr *intrin) cluster_size, x_hi); scan_low = nir_u2u64(b, scan_low); - scan_mid = nir_ishl(b, nir_u2u64(b, scan_mid), nir_imm_int(b, 24)); - scan_hi = nir_ishl(b, nir_u2u64(b, scan_hi), nir_imm_int(b, 48)); + scan_mid = nir_ishl_imm(b, nir_u2u64(b, scan_mid), 24); + scan_hi = nir_ishl_imm(b, nir_u2u64(b, scan_hi), 48); return nir_iadd(b, scan_hi, nir_iadd(b, scan_mid, scan_low)); } diff --git a/src/microsoft/compiler/dxil_nir.c b/src/microsoft/compiler/dxil_nir.c index 41440dd6093..b558a55f2c8 100644 --- a/src/microsoft/compiler/dxil_nir.c +++ b/src/microsoft/compiler/dxil_nir.c @@ -105,8 +105,7 @@ lower_32b_offset_load(nir_builder *b, nir_intrinsic_instr *intr, nir_variable *v */ if (num_bits <= 16) { nir_ssa_def *shift = - nir_imul(b, nir_iand(b, offset, nir_imm_int(b, 3)), - nir_imm_int(b, 8)); + nir_imul_imm(b, nir_iand_imm(b, offset, 3), 8); vec32 = nir_ushr(b, vec32, shift); } @@ -133,7 +132,7 @@ lower_masked_store_vec32(nir_builder *b, nir_ssa_def *offset, nir_ssa_def *index /* If we have small alignments, we need to place them correctly in the u32 component. */ if (alignment <= 2) { nir_ssa_def *shift = - nir_imul_imm(b, nir_iand(b, offset, nir_imm_int(b, 3)), 8); + nir_imul_imm(b, nir_iand_imm(b, offset, 3), 8); vec32 = nir_ishl(b, vec32, shift); mask = nir_ishl(b, mask, shift);