From 8a6903e50d344fb46027963975dc149f0f6b0fa8 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Mon, 5 Aug 2024 19:36:02 -0700 Subject: [PATCH] intel/brw: Rename lsc_aop_for_nir_intrinsic to "op" instead of "aop" This is going to handle more than atomics shortly. Reviewed-by: Lionel Landwerlin Reviewed-by: Caio Oliveira Reviewed-by: Rohan Garg Part-of: --- src/intel/compiler/brw_fs_nir.cpp | 6 +++--- src/intel/compiler/brw_nir.c | 10 +++++----- src/intel/compiler/brw_nir.h | 2 +- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 7d50a34e6af..40d47ae5540 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -6166,7 +6166,7 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, brw_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS); } else { unsigned num_srcs = info->num_srcs; - enum lsc_opcode op = lsc_aop_for_nir_intrinsic(instr); + enum lsc_opcode op = lsc_op_for_nir_intrinsic(instr); if (op == LSC_OP_ATOMIC_INC || op == LSC_OP_ATOMIC_DEC) { assert(num_srcs == 4); num_srcs = 3; @@ -8075,7 +8075,7 @@ fs_nir_emit_surface_atomic(nir_to_brw_state &ntb, const fs_builder &bld, { const intel_device_info *devinfo = ntb.devinfo; - enum lsc_opcode op = lsc_aop_for_nir_intrinsic(instr); + enum lsc_opcode op = lsc_op_for_nir_intrinsic(instr); int num_data = lsc_op_num_data_values(op); bool shared = surface.file == IMM && surface.ud == GFX7_BTI_SLM; @@ -8142,7 +8142,7 @@ static void fs_nir_emit_global_atomic(nir_to_brw_state &ntb, const fs_builder &bld, nir_intrinsic_instr *instr) { - enum lsc_opcode op = lsc_aop_for_nir_intrinsic(instr); + enum lsc_opcode op = lsc_op_for_nir_intrinsic(instr); int num_data = lsc_op_num_data_values(op); brw_reg dest = get_nir_def(ntb, instr->def); diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index aee08228428..b344a9a9601 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler/brw_nir.c @@ -2038,12 +2038,12 @@ brw_cmod_for_nir_comparison(nir_op op) } enum lsc_opcode -lsc_aop_for_nir_intrinsic(const nir_intrinsic_instr *atomic) +lsc_op_for_nir_intrinsic(const nir_intrinsic_instr *intrin) { - switch (nir_intrinsic_atomic_op(atomic)) { + switch (nir_intrinsic_atomic_op(intrin)) { case nir_atomic_op_iadd: { unsigned src_idx; - switch (atomic->intrinsic) { + switch (intrin->intrinsic) { case nir_intrinsic_image_atomic: case nir_intrinsic_bindless_image_atomic: src_idx = 3; @@ -2059,8 +2059,8 @@ lsc_aop_for_nir_intrinsic(const nir_intrinsic_instr *atomic) unreachable("Invalid add atomic opcode"); } - if (nir_src_is_const(atomic->src[src_idx])) { - int64_t add_val = nir_src_as_int(atomic->src[src_idx]); + if (nir_src_is_const(intrin->src[src_idx])) { + int64_t add_val = nir_src_as_int(intrin->src[src_idx]); if (add_val == 1) return LSC_OP_ATOMIC_INC; else if (add_val == -1) diff --git a/src/intel/compiler/brw_nir.h b/src/intel/compiler/brw_nir.h index 4481c079945..935d12f3087 100644 --- a/src/intel/compiler/brw_nir.h +++ b/src/intel/compiler/brw_nir.h @@ -204,7 +204,7 @@ unsigned brw_nir_api_subgroup_size(const nir_shader *nir, unsigned hw_subgroup_size); enum brw_conditional_mod brw_cmod_for_nir_comparison(nir_op op); -enum lsc_opcode lsc_aop_for_nir_intrinsic(const nir_intrinsic_instr *atomic); +enum lsc_opcode lsc_op_for_nir_intrinsic(const nir_intrinsic_instr *intrin); enum brw_reg_type brw_type_for_nir_type(const struct intel_device_info *devinfo, nir_alu_type type);