diff --git a/src/broadcom/vulkan/v3dv_cmd_buffer.c b/src/broadcom/vulkan/v3dv_cmd_buffer.c
index 37688859e91..482289bc08e 100644
--- a/src/broadcom/vulkan/v3dv_cmd_buffer.c
+++ b/src/broadcom/vulkan/v3dv_cmd_buffer.c
@@ -3008,7 +3008,8 @@ v3dv_cmd_buffer_emit_pre_draw(struct v3dv_cmd_buffer *cmd_buffer,
        BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_RS_FRONT_FACE) ||
        BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_DS_STENCIL_TEST_ENABLE) ||
        BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_DS_DEPTH_BOUNDS_TEST_ENABLE) ||
-       BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_RS_DEPTH_BIAS_ENABLE)) {
+       BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_RS_DEPTH_BIAS_ENABLE) ||
+       BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_RS_RASTERIZER_DISCARD_ENABLE)) {
       v3dv_X(device, cmd_buffer_emit_configuration_bits)(cmd_buffer);
    }
 
diff --git a/src/broadcom/vulkan/v3dv_pipeline.c b/src/broadcom/vulkan/v3dv_pipeline.c
index 8b4f1e56e11..c0b2edbb04d 100644
--- a/src/broadcom/vulkan/v3dv_pipeline.c
+++ b/src/broadcom/vulkan/v3dv_pipeline.c
@@ -1102,10 +1102,10 @@ static const enum pipe_logicop vk_to_pipe_logicop[] = {
 };
 
 static bool
-enable_line_smooth(uint8_t topology,
+enable_line_smooth(struct v3dv_pipeline *pipeline,
                    const VkPipelineRasterizationStateCreateInfo *rs_info)
 {
-   if (!rs_info || rs_info->rasterizerDiscardEnable)
+   if (!pipeline->rasterization_enabled)
       return false;
 
    const VkPipelineRasterizationLineStateCreateInfoKHR *ls_info =
@@ -1115,7 +1115,11 @@ enable_line_smooth(uint8_t topology,
    if (!ls_info)
       return false;
 
-   switch(topology) {
+   /* Although topology is dynamic now, the topology class can't change
+    * because we don't support dynamicPrimitiveTopologyUnrestricted, so we can
+    * use the static topology from the pipeline for this.
+    */
+   switch(pipeline->topology) {
    case MESA_PRIM_LINES:
    case MESA_PRIM_LINE_LOOP:
    case MESA_PRIM_LINE_STRIP:
@@ -1203,22 +1207,18 @@ pipeline_populate_v3d_fs_key(struct v3d_fs_key *key,
    key->has_gs = has_geometry_shader;
 
    const VkPipelineColorBlendStateCreateInfo *cb_info =
-      !pCreateInfo->pRasterizationState->rasterizerDiscardEnable ?
+      p_stage->pipeline->rasterization_enabled ?
       pCreateInfo->pColorBlendState : NULL;
 
    key->logicop_func = cb_info && cb_info->logicOpEnable == VK_TRUE ?
                        vk_to_pipe_logicop[cb_info->logicOp] :
                        PIPE_LOGICOP_COPY;
 
-   const bool raster_enabled =
-      pCreateInfo->pRasterizationState &&
-      !pCreateInfo->pRasterizationState->rasterizerDiscardEnable;
-
    /* Multisample rasterization state must be ignored if rasterization
     * is disabled.
     */
    const VkPipelineMultisampleStateCreateInfo *ms_info =
-      raster_enabled ? pCreateInfo->pMultisampleState : NULL;
+      p_stage->pipeline->rasterization_enabled ? pCreateInfo->pMultisampleState : NULL;
    if (ms_info) {
       assert(ms_info->rasterizationSamples == VK_SAMPLE_COUNT_1_BIT ||
              ms_info->rasterizationSamples == VK_SAMPLE_COUNT_4_BIT);
@@ -1230,7 +1230,8 @@ pipeline_populate_v3d_fs_key(struct v3d_fs_key *key,
       key->sample_alpha_to_one = ms_info->alphaToOneEnable;
    }
 
-   key->line_smoothing = enable_line_smooth(topology, pCreateInfo->pRasterizationState);
+   key->line_smoothing = enable_line_smooth(p_stage->pipeline,
+                                            pCreateInfo->pRasterizationState);
 
    /* This is intended for V3D versions before 4.1, otherwise we just use the
     * tile buffer load/store swap R/B bit.
@@ -1988,16 +1989,12 @@ pipeline_populate_graphics_key(struct v3dv_pipeline *pipeline,
 
    key->line_smooth = pipeline->line_smooth;
 
-   const bool raster_enabled =
-      pCreateInfo->pRasterizationState &&
-      !pCreateInfo->pRasterizationState->rasterizerDiscardEnable;
-
    const VkPipelineInputAssemblyStateCreateInfo *ia_info =
       pCreateInfo->pInputAssemblyState;
    key->topology = vk_to_mesa_prim[ia_info->topology];
 
    const VkPipelineColorBlendStateCreateInfo *cb_info =
-      raster_enabled ? pCreateInfo->pColorBlendState : NULL;
+      pipeline->rasterization_enabled ? pCreateInfo->pColorBlendState : NULL;
 
    key->logicop_func = cb_info && cb_info->logicOpEnable == VK_TRUE ?
       vk_to_pipe_logicop[cb_info->logicOp] :
@@ -2007,7 +2004,7 @@ pipeline_populate_graphics_key(struct v3dv_pipeline *pipeline,
     * is disabled.
     */
    const VkPipelineMultisampleStateCreateInfo *ms_info =
-      raster_enabled ? pCreateInfo->pMultisampleState : NULL;
+      pipeline->rasterization_enabled ? pCreateInfo->pMultisampleState : NULL;
    if (ms_info) {
       assert(ms_info->rasterizationSamples == VK_SAMPLE_COUNT_1_BIT ||
              ms_info->rasterizationSamples == VK_SAMPLE_COUNT_4_BIT);
@@ -2828,8 +2825,7 @@ static VkResult
 pipeline_init_dynamic_state(struct v3dv_device *device,
                             struct v3dv_pipeline *pipeline,
                             struct vk_graphics_pipeline_state *pipeline_state,
-                            const VkGraphicsPipelineCreateInfo *pCreateInfo,
-                            const VkPipelineColorWriteCreateInfoEXT *cw_info)
+                            const VkGraphicsPipelineCreateInfo *pCreateInfo)
 {
    VkResult result = VK_SUCCESS;
    struct vk_graphics_pipeline_all_state all;
@@ -2857,11 +2853,13 @@ pipeline_init_dynamic_state(struct v3dv_device *device,
 
    v3dv_dyn->color_write_enable =
       (1ull << (4 * V3D_MAX_RENDER_TARGETS(device->devinfo.ver))) - 1;
-   if (cw_info && BITSET_TEST(dyn->set, MESA_VK_DYNAMIC_CB_COLOR_WRITE_ENABLES)) {
+   if (pipeline_state->cb) {
+      const uint8_t color_writes = pipeline_state->cb->color_write_enables;
       v3dv_dyn->color_write_enable = 0;
-      for (uint32_t i = 0; i < cw_info->attachmentCount; i++)
+      for (uint32_t i = 0; i < pipeline_state->cb->attachment_count; i++) {
          v3dv_dyn->color_write_enable |=
-            cw_info->pColorWriteEnables[i] ? (0xfu << (i * 4)) : 0;
+            (color_writes & BITFIELD_BIT(i)) ? (0xfu << (i * 4)) : 0;
+      }
    }
 
    return result;
@@ -2896,12 +2894,23 @@ pipeline_init(struct v3dv_pipeline *pipeline,
       pCreateInfo->pInputAssemblyState;
    pipeline->topology = vk_to_mesa_prim[ia_info->topology];
 
-   /* If rasterization is not enabled, various CreateInfo structs must be
-    * ignored.
+   struct vk_graphics_pipeline_state pipeline_state = { };
+   result = pipeline_init_dynamic_state(device, pipeline, &pipeline_state,
+                                        pCreateInfo);
+
+   if (result != VK_SUCCESS) {
+      /* Caller would already destroy the pipeline, and we didn't allocate any
+       * extra info. We don't need to do anything else.
+       */
+      return result;
+   }
+
+   /* If rasterization is disabled, we just disable it through the CFG_BITS
+    * packet, so for building the pipeline we always assume it is enabled
     */
    const bool raster_enabled =
-      pCreateInfo->pRasterizationState &&
-      !pCreateInfo->pRasterizationState->rasterizerDiscardEnable;
+      (pipeline_state.rs && !pipeline_state.rs->rasterizer_discard_enable) ||
+      BITSET_TEST(pipeline_state.dynamic, MESA_VK_DYNAMIC_RS_RASTERIZER_DISCARD_ENABLE);
 
    pipeline->rasterization_enabled = raster_enabled;
 
@@ -2932,22 +2941,6 @@ pipeline_init(struct v3dv_pipeline *pipeline,
    const VkPipelineMultisampleStateCreateInfo *ms_info =
       raster_enabled ? pCreateInfo->pMultisampleState : NULL;
 
-   const VkPipelineColorWriteCreateInfoEXT *cw_info =
-      cb_info ? vk_find_struct_const(cb_info->pNext,
-                                     PIPELINE_COLOR_WRITE_CREATE_INFO_EXT) :
-                NULL;
-
-   struct vk_graphics_pipeline_state pipeline_state = { };
-   result = pipeline_init_dynamic_state(device, pipeline, &pipeline_state,
-                                        pCreateInfo, cw_info);
-
-   if (result != VK_SUCCESS) {
-      /* Caller would already destroy the pipeline, and we didn't allocate any
-       * extra info. We don't need to do anything else.
-       */
-      return result;
-   }
-
    const VkPipelineViewportDepthClipControlCreateInfoEXT *depth_clip_control =
       vp_info ? vk_find_struct_const(vp_info->pNext,
                                      PIPELINE_VIEWPORT_DEPTH_CLIP_CONTROL_CREATE_INFO_EXT) :
@@ -2963,7 +2956,7 @@ pipeline_init(struct v3dv_pipeline *pipeline,
 
    pipeline_set_sample_mask(pipeline, ms_info);
    pipeline_set_sample_rate_shading(pipeline, ms_info);
-   pipeline->line_smooth = enable_line_smooth(pipeline->topology, rs_info);
+   pipeline->line_smooth = enable_line_smooth(pipeline, rs_info);
 
    result = pipeline_compile_graphics(pipeline, cache, pCreateInfo, pAllocator);
 
diff --git a/src/broadcom/vulkan/v3dvx_cmd_buffer.c b/src/broadcom/vulkan/v3dvx_cmd_buffer.c
index a5a7f3f4832..6f979ee9291 100644
--- a/src/broadcom/vulkan/v3dvx_cmd_buffer.c
+++ b/src/broadcom/vulkan/v3dvx_cmd_buffer.c
@@ -2010,7 +2010,7 @@ v3dX(cmd_buffer_emit_configuration_bits)(struct v3dv_cmd_buffer *cmd_buffer)
          cmd_buffer->state.z_updates_enable;
 #endif
 
-      if (pipeline->rasterization_enabled) {
+      if (!dyn->rs.rasterizer_discard_enable) {
          assert(BITSET_TEST(dyn->set, MESA_VK_DYNAMIC_RS_CULL_MODE));
          assert(BITSET_TEST(dyn->set, MESA_VK_DYNAMIC_RS_FRONT_FACE));
          config.enable_forward_facing_primitive = !(dyn->rs.cull_mode & VK_CULL_MODE_FRONT_BIT);
@@ -2037,6 +2037,7 @@ v3dX(cmd_buffer_emit_configuration_bits)(struct v3dv_cmd_buffer *cmd_buffer)
    BITSET_CLEAR(dyn->dirty, MESA_VK_DYNAMIC_DS_DEPTH_BOUNDS_TEST_ENABLE);
    BITSET_CLEAR(dyn->dirty, MESA_VK_DYNAMIC_DS_STENCIL_TEST_ENABLE);
    BITSET_CLEAR(dyn->dirty, MESA_VK_DYNAMIC_RS_DEPTH_BIAS_ENABLE);
+   BITSET_CLEAR(dyn->dirty, MESA_VK_DYNAMIC_RS_RASTERIZER_DISCARD_ENABLE);
 }
 
 void