diff --git a/src/intel/genxml/gen125.xml b/src/intel/genxml/gen125.xml
index a33876bfee4..13e861ac492 100644
--- a/src/intel/genxml/gen125.xml
+++ b/src/intel/genxml/gen125.xml
@@ -1892,11 +1892,17 @@
       <value name="Max 56" value="2" />
       <value name="Max 48" value="3" />
     </field>
-    <field name="Force Non-Coherent" start="35" end="36" type="uint">
+    <field name="Force Non-Coherent DG2" start="35" end="36" type="uint">
       <value name="Force Disabled" value="0" />
       <value name="Force CPU Non-Coherent" value="1" />
       <value name="Force GPU Non-Coherent" value="2" />
     </field>
+    <field name="Z Async Throttle settings" start="35" end="36" type="uint" prefix="ZATS">
+      <value name="Defer to Pixel Async Compute Thread Limit" value="0" />
+      <value name="Max 32" value="1" />
+      <value name="Max 40" value="2" />
+      <value name="Max 48" value="3" />
+    </field>
     <field name="Fast Clear Disabled on Compressed Surface" start="37" end="37" type="bool" />
     <field name="Disable SLM Read Merge Optimization" start="38" end="38" type="bool" />
     <field name="Pixel Async Compute Thread Limit" start="39" end="41" type="uint" prefix="PACTL">
@@ -1914,7 +1920,8 @@
     <field name="Large GRF Mode" start="47" end="47" type="bool" />
     <field name="Z Pass Async Compute Thread Limit Mask" start="48" end="50" type="uint" />
     <field name="Mask1" start="48" end="63" type="uint" />
-    <field name="Force Non-Coherent Mask" start="51" end="52" type="uint" />
+    <field name="Force Non-Coherent DG2 Mask" start="51" end="52" type="uint" />
+    <field name="Z Async Throttle settings Mask" start="51" end="52" type="uint" />
     <field name="Fast Clear Disabled on Compressed Surface Mask" start="53" end="53" type="bool" />
     <field name="Disable SLM Read Merge Optimization Mask" start="54" end="54" type="bool" />
     <field name="Pixel Async Compute Thread Limit Mask" start="55" end="57" type="uint" />