diff --git a/src/intel/compiler/brw_rt.h b/src/intel/compiler/brw_rt.h
index 15c024072f1..2cf1851ff59 100644
--- a/src/intel/compiler/brw_rt.h
+++ b/src/intel/compiler/brw_rt.h
@@ -24,6 +24,11 @@
 #ifndef BRW_RT_H
 #define BRW_RT_H
 
+#include <stdint.h>
+
+#include "compiler/shader_enums.h"
+#include "util/macros.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -194,8 +199,8 @@ struct brw_rt_raygen_trampoline_params {
 #define BRW_RT_OFFSETOF_HIT_ATTRIB_DATA BRW_RT_SIZEOF_HW_STACK
 
 #define BRW_RT_ASYNC_STACK_STRIDE \
-   ALIGN(BRW_RT_OFFSETOF_HIT_ATTRIB_DATA + \
-         BRW_RT_SIZEOF_HIT_ATTRIB_DATA, 64)
+   ALIGN_POT(BRW_RT_OFFSETOF_HIT_ATTRIB_DATA + \
+             BRW_RT_SIZEOF_HIT_ATTRIB_DATA, 64)
 
 static inline void
 brw_rt_compute_scratch_layout(struct brw_rt_scratch_layout *layout,
diff --git a/src/intel/tools/intel_context.h b/src/intel/tools/intel_context.h
index 8740dfe554e..d9c747221bc 100644
--- a/src/intel/tools/intel_context.h
+++ b/src/intel/tools/intel_context.h
@@ -26,6 +26,8 @@
 
 #include <stdint.h>
 
+#include "util/macros.h"
+
 #define RING_SIZE         (1 * 4096)
 #define PPHWSP_SIZE         (1 * 4096)
 
@@ -72,8 +74,8 @@
 #define PTE_SIZE 4
 #define GFX8_PTE_SIZE 8
 
-#define NUM_PT_ENTRIES (ALIGN(MEMORY_MAP_SIZE, 4096) / 4096)
-#define PT_SIZE ALIGN(NUM_PT_ENTRIES * GFX8_PTE_SIZE, 4096)
+#define NUM_PT_ENTRIES (ALIGN_POT(MEMORY_MAP_SIZE, 4096) / 4096)
+#define PT_SIZE ALIGN_POT(NUM_PT_ENTRIES * GFX8_PTE_SIZE, 4096)
 
 #define CONTEXT_FLAGS (0x339)   /* Normal Priority | L3-LLC Coherency |
                                  * PPGTT Enabled |