diff --git a/src/amd/compiler/instruction_selection/aco_select_nir_alu.cpp b/src/amd/compiler/instruction_selection/aco_select_nir_alu.cpp
index aaeef4cb619..ede133d7732 100644
--- a/src/amd/compiler/instruction_selection/aco_select_nir_alu.cpp
+++ b/src/amd/compiler/instruction_selection/aco_select_nir_alu.cpp
@@ -1187,10 +1187,34 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr)
       break;
    }
    case nir_op_bitfield_reverse: {
+      Temp src = get_alu_src(ctx, instr->src[0]);
       if (dst.regClass() == s1) {
-         bld.sop1(aco_opcode::s_brev_b32, Definition(dst), get_alu_src(ctx, instr->src[0]));
-      } else if (dst.regClass() == v1) {
-         bld.vop1(aco_opcode::v_bfrev_b32, Definition(dst), get_alu_src(ctx, instr->src[0]));
+         Temp rev = bld.sop1(aco_opcode::s_brev_b32, bld.def(s1), src);
+
+         if (instr->def.bit_size != 32) {
+            bld.pseudo(aco_opcode::p_extract, Definition(dst), bld.def(s1, scc), rev,
+                       Operand::c32(instr->def.bit_size == 8 ? 3 : 1),
+                       Operand::c32(instr->def.bit_size), Operand::zero());
+         } else {
+            bld.copy(Definition(dst), rev);
+         }
+      } else if (dst.regClass() == s2) {
+         bld.sop1(aco_opcode::s_brev_b64, Definition(dst), src);
+      } else if (dst.regClass() == v1 || dst.regClass() == v1b || dst.regClass() == v2b) {
+         Temp rev = bld.vop1(aco_opcode::v_bfrev_b32, bld.def(v1), src);
+
+         if (instr->def.bit_size != 32) {
+            bld.pseudo(aco_opcode::p_extract_vector, Definition(dst), rev,
+                       Operand::c32(instr->def.bit_size == 8 ? 3 : 1));
+         } else {
+            bld.copy(Definition(dst), rev);
+         }
+      } else if (dst.regClass() == v2) {
+         Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
+         bld.pseudo(aco_opcode::p_split_vector, Definition(hi), Definition(lo), src);
+         lo = bld.vop1(aco_opcode::v_bfrev_b32, bld.def(v1), lo);
+         hi = bld.vop1(aco_opcode::v_bfrev_b32, bld.def(v1), hi);
+         bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
       } else {
          isel_err(&instr->instr, "Unimplemented NIR instr bit size");
       }