intel/fs/xe2+: Pass correct dispatch_width to fs_generator for geometry-processing stages.

Instead of hard-coding a dispatch_width value which is no longer
correct on Xe2+.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26605>

src/intel/compiler/brw_vec4_tcs.cpp

@@ -470,7 +470,7 @@ brw_compile_tcs(const struct brw_compiler *compiler,
                                         nir->info.name));
       }
 
-      g.generate_code(v.cfg, 8, v.shader_stats,
+      g.generate_code(v.cfg, dispatch_width, v.shader_stats,
                       v.performance_analysis.require(), params->base.stats);
 
       g.add_const_data(nir->constant_data, nir->constant_data_size);