From 84895dba7fd607c2691f4b70d31f02516ebb89d3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Tue, 13 Apr 2021 21:37:40 -0400 Subject: [PATCH] amd: remove some references to older LLVM versions in comments Reviewed-by: Samuel Pitoiset Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/amd/llvm/ac_llvm_util.c | 2 -- src/amd/llvm/ac_nir_to_llvm.c | 9 +-------- src/gallium/drivers/radeonsi/si_get.c | 2 +- src/gallium/drivers/radeonsi/si_pipe.c | 4 +--- src/gallium/drivers/radeonsi/si_shader.c | 7 +------ src/gallium/drivers/radeonsi/si_shader_llvm_vs.c | 3 --- 6 files changed, 4 insertions(+), 23 deletions(-) diff --git a/src/amd/llvm/ac_llvm_util.c b/src/amd/llvm/ac_llvm_util.c index f8d8c2d329d..c684200a34f 100644 --- a/src/amd/llvm/ac_llvm_util.c +++ b/src/amd/llvm/ac_llvm_util.c @@ -67,9 +67,7 @@ static void ac_init_llvm_target(void) "mesa", "-simplifycfg-sink-common=false", "-global-isel-abort=2", - /* Atomic optimizations require LLVM 10.0 for gfx10 support. */ "-amdgpu-atomic-optimizations=true", - /* This was disabled by default in: https://reviews.llvm.org/D77228 */ "-structurizecfg-skip-uniform-regions", }; LLVMParseCommandLineOptions(ARRAY_SIZE(argv), argv, NULL); diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c index 2309e015893..2080dec62e4 100644 --- a/src/amd/llvm/ac_nir_to_llvm.c +++ b/src/amd/llvm/ac_nir_to_llvm.c @@ -1730,8 +1730,6 @@ static void visit_store_ssbo(struct ac_nir_context *ctx, nir_intrinsic_instr *in u_bit_scan_consecutive_range(&writemask, &start, &count); - /* Due to an LLVM limitation with LLVM < 9, split 3-element - * writes into a 2-element and a 1-element write. */ if (count == 3 && (elem_size_bytes != 4 || !ac_has_vec3_support(ctx->ac.chip_class, false))) { writemask |= 1 << (start + 2); count = 2; @@ -2674,9 +2672,6 @@ static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx, const nir_int if (cmpswap && instr->dest.ssa.bit_size == 64) { result = emit_ssbo_comp_swap_64(ctx, params[2], params[3], params[1], params[0], true); } else { - /* XXX: The new raw/struct atomic intrinsics are buggy - * with LLVM 8, see r358579. - */ params[param_count++] = ctx->ac.i32_0; /* soffset */ params[param_count++] = ctx->ac.i32_0; /* slc */ @@ -5136,9 +5131,7 @@ bool ac_lower_indirect_derefs(struct nir_shader *nir, enum chip_class chip_class NIR_PASS(progress, nir, nir_lower_vars_to_scratch, nir_var_function_temp, 256, glsl_get_natural_size_align_bytes); - /* While it would be nice not to have this flag, we are constrained - * by the reality that LLVM 9.0 has buggy VGPR indexing on GFX9. - */ + /* LLVM doesn't support VGPR indexing on GFX9. */ bool llvm_has_working_vgpr_indexing = chip_class != GFX9; /* TODO: Indirect indexing of GS inputs is unimplemented. diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c index 2924498b9e9..13f06ea07d2 100644 --- a/src/gallium/drivers/radeonsi/si_get.c +++ b/src/gallium/drivers/radeonsi/si_get.c @@ -709,7 +709,7 @@ static unsigned get_max_threads_per_block(struct si_screen *screen, enum pipe_sh if (ir_type == PIPE_SHADER_IR_NATIVE) return 256; - /* LLVM 10 only supports 1024 threads per block. */ + /* LLVM only supports 1024 threads per block. */ return 1024; } diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 7f23d8474ab..483258d075e 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -1266,9 +1266,7 @@ static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws, sscreen->pbb_persistent_states_per_bin <= 32); } - /* While it would be nice not to have this flag, we are constrained - * by the reality that LLVM 9.0 has buggy VGPR indexing on GFX9. - */ + /* LLVM doesn't support VGPR indexing on GFX9. */ sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class != GFX9; (void)simple_mtx_init(&sscreen->shader_parts_mutex, mtx_plain); diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index 121feb6fbd7..763223b3cc1 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -793,9 +793,6 @@ static bool si_shader_binary_open(struct si_screen *screen, struct si_shader *sh if (sel && screen->info.chip_class >= GFX9 && !shader->is_gs_copy_shader && (sel->info.stage == MESA_SHADER_GEOMETRY || shader->key.as_ngg)) { - /* We add this symbol even on LLVM <= 8 to ensure that - * shader->config.lds_size is set correctly below. - */ struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++]; sym->name = "esgs_ring"; sym->size = shader->gs_info.esgs_ring_size * 4; @@ -1465,9 +1462,7 @@ bool si_compile_shader(struct si_screen *sscreen, struct ac_llvm_compiler *compi if (!si_llvm_compile_shader(sscreen, compiler, shader, debug, nir, free_nir)) return false; - /* Validate SGPR and VGPR usage for compute to detect compiler bugs. - * LLVM 3.9svn has this bug. - */ + /* Validate SGPR and VGPR usage for compute to detect compiler bugs. */ if (sel->info.stage == MESA_SHADER_COMPUTE) { unsigned wave_size = sscreen->compute_wave_size; unsigned max_vgprs = diff --git a/src/gallium/drivers/radeonsi/si_shader_llvm_vs.c b/src/gallium/drivers/radeonsi/si_shader_llvm_vs.c index 6b073eca3d9..602fce165ec 100644 --- a/src/gallium/drivers/radeonsi/si_shader_llvm_vs.c +++ b/src/gallium/drivers/radeonsi/si_shader_llvm_vs.c @@ -117,9 +117,6 @@ static void load_input_vs(struct si_shader_context *ctx, unsigned input_index, L /* Use the open-coded implementation for all loads of doubles and * of dword-sized data that needs fixups. We need to insert conversion * code anyway, and the amd/common code does it for us. - * - * Note: On LLVM <= 8, we can only open-code formats with - * channel size >= 4 bytes. */ bool opencode = ctx->shader->key.mono.vs_fetch_opencode & (1 << input_index); fix_fetch.bits = ctx->shader->key.mono.vs_fix_fetch[input_index].bits;