diff --git a/src/gallium/drivers/radeonsi/gfx11_query.c b/src/gallium/drivers/radeonsi/gfx11_query.c
index 4e01b06e307..28b69328bee 100644
--- a/src/gallium/drivers/radeonsi/gfx11_query.c
+++ b/src/gallium/drivers/radeonsi/gfx11_query.c
@@ -348,7 +348,7 @@ static void gfx11_sh_query_get_result_resource(struct si_context *sctx, struct s
 
    /* TODO: Range-invalidate GL2 */
    if (sctx->screen->info.cp_sdma_ge_use_system_memory_scope) {
-      sctx->flags |= SI_CONTEXT_INV_L2;
+      sctx->barrier_flags |= SI_CONTEXT_INV_L2;
       si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
    }
 
diff --git a/src/gallium/drivers/radeonsi/si_barrier.c b/src/gallium/drivers/radeonsi/si_barrier.c
index dd46c3fcd22..e199b6454dd 100644
--- a/src/gallium/drivers/radeonsi/si_barrier.c
+++ b/src/gallium/drivers/radeonsi/si_barrier.c
@@ -61,7 +61,7 @@ static void gfx10_emit_barrier(struct si_context *ctx, struct radeon_cmdbuf *cs)
 {
    uint32_t gcr_cntl = 0;
    unsigned cb_db_event = 0;
-   unsigned flags = ctx->flags;
+   unsigned flags = ctx->barrier_flags;
 
    if (!flags)
       return;
@@ -241,12 +241,12 @@ static void gfx10_emit_barrier(struct si_context *ctx, struct radeon_cmdbuf *cs)
    }
    radeon_end();
 
-   ctx->flags = 0;
+   ctx->barrier_flags = 0;
 }
 
 static void gfx6_emit_barrier(struct si_context *sctx, struct radeon_cmdbuf *cs)
 {
-   uint32_t flags = sctx->flags;
+   uint32_t flags = sctx->barrier_flags;
 
    if (!flags)
       return;
@@ -405,7 +405,7 @@ static void gfx6_emit_barrier(struct si_context *sctx, struct radeon_cmdbuf *cs)
       si_cp_wait_mem(sctx, cs, va, sctx->wait_mem_number, 0xffffffff, WAIT_REG_MEM_EQUAL);
 
       if (unlikely(sctx->sqtt_enabled)) {
-         si_sqtt_describe_barrier_end(sctx, cs, sctx->flags);
+         si_sqtt_describe_barrier_end(sctx, cs, sctx->barrier_flags);
       }
    }
 
@@ -481,7 +481,7 @@ static void gfx6_emit_barrier(struct si_context *sctx, struct radeon_cmdbuf *cs)
       sctx->pipeline_stats_enabled = 0;
    }
 
-   sctx->flags = 0;
+   sctx->barrier_flags = 0;
 }
 
 static void si_emit_barrier_as_atom(struct si_context *sctx, unsigned index)
@@ -533,12 +533,12 @@ void si_barrier_before_internal_op(struct si_context *sctx, unsigned flags,
       if (!si_is_buffer_idle(sctx, buf, RADEON_USAGE_WRITE |
                              (writable_buffers_mask & BITFIELD_BIT(i) ? RADEON_USAGE_READ : 0))) {
          if (buf->bind_history & ps_mask)
-            sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH;
+            sctx->barrier_flags |= SI_CONTEXT_PS_PARTIAL_FLUSH;
          else
-            sctx->flags |= SI_CONTEXT_VS_PARTIAL_FLUSH;
+            sctx->barrier_flags |= SI_CONTEXT_VS_PARTIAL_FLUSH;
 
          if (buf->bind_history & cs_mask)
-            sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
+            sctx->barrier_flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
       }
    }
 
@@ -553,12 +553,12 @@ void si_barrier_before_internal_op(struct si_context *sctx, unsigned flags,
       if (!si_is_buffer_idle(sctx, img, RADEON_USAGE_WRITE | (writable ? RADEON_USAGE_READ : 0))) {
          si_make_CB_shader_coherent(sctx, images[i].resource->nr_samples, true,
                ((struct si_texture*)images[i].resource)->surface.u.gfx9.color.dcc.pipe_aligned);
-         sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_CS_PARTIAL_FLUSH;
+         sctx->barrier_flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_CS_PARTIAL_FLUSH;
       }
    }
 
    /* Invalidate the VMEM cache only. The SMEM cache isn't used by shader buffers. */
-   sctx->flags |= SI_CONTEXT_INV_VCACHE;
+   sctx->barrier_flags |= SI_CONTEXT_INV_VCACHE;
    si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
 }
 
@@ -569,18 +569,18 @@ void si_barrier_after_internal_op(struct si_context *sctx, unsigned flags,
                                   unsigned num_images,
                                   const struct pipe_image_view *images)
 {
-   sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
+   sctx->barrier_flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
 
    if (num_images) {
       /* Make sure image stores are visible to CB, which doesn't use L2 on GFX6-8. */
-      sctx->flags |= sctx->gfx_level <= GFX8 ? SI_CONTEXT_WB_L2 : 0;
+      sctx->barrier_flags |= sctx->gfx_level <= GFX8 ? SI_CONTEXT_WB_L2 : 0;
       /* Make sure image stores are visible to all CUs. */
-      sctx->flags |= SI_CONTEXT_INV_VCACHE;
+      sctx->barrier_flags |= SI_CONTEXT_INV_VCACHE;
    }
 
    /* Make sure buffer stores are visible to all CUs and also as index/indirect buffers. */
    if (num_buffers)
-      sctx->flags |= SI_CONTEXT_INV_SCACHE | SI_CONTEXT_INV_VCACHE | SI_CONTEXT_PFP_SYNC_ME;
+      sctx->barrier_flags |= SI_CONTEXT_INV_SCACHE | SI_CONTEXT_INV_VCACHE | SI_CONTEXT_PFP_SYNC_ME;
 
    /* We must set L2_cache_dirty for buffers because:
     * - GFX6,12: CP DMA doesn't use L2.
@@ -600,7 +600,7 @@ void si_barrier_after_internal_op(struct si_context *sctx, unsigned flags,
              images[i].access & PIPE_IMAGE_ACCESS_WRITE &&
              (sctx->screen->always_allow_dcc_stores ||
               images[i].access & SI_IMAGE_ACCESS_ALLOW_DCC_STORE)) {
-            sctx->flags |= SI_CONTEXT_INV_L2;
+            sctx->barrier_flags |= SI_CONTEXT_INV_L2;
             break;
          }
       }
@@ -668,10 +668,10 @@ static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
    if (!flags)
       return;
 
-   sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_CS_PARTIAL_FLUSH;
+   sctx->barrier_flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_CS_PARTIAL_FLUSH;
 
    if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
-      sctx->flags |= SI_CONTEXT_INV_SCACHE | SI_CONTEXT_INV_VCACHE;
+      sctx->barrier_flags |= SI_CONTEXT_INV_SCACHE | SI_CONTEXT_INV_VCACHE;
 
    /* VMEM cache contents are written back to L2 automatically at the end of waves, but
     * the contents of other VMEM caches might still be stale.
@@ -680,38 +680,38 @@ static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
     */
    if (flags & (PIPE_BARRIER_VERTEX_BUFFER | PIPE_BARRIER_SHADER_BUFFER | PIPE_BARRIER_TEXTURE |
                 PIPE_BARRIER_IMAGE | PIPE_BARRIER_STREAMOUT_BUFFER | PIPE_BARRIER_GLOBAL_BUFFER))
-      sctx->flags |= SI_CONTEXT_INV_VCACHE;
+      sctx->barrier_flags |= SI_CONTEXT_INV_VCACHE;
 
    if (flags & (PIPE_BARRIER_INDEX_BUFFER | PIPE_BARRIER_INDIRECT_BUFFER))
-      sctx->flags |= SI_CONTEXT_PFP_SYNC_ME;
+      sctx->barrier_flags |= SI_CONTEXT_PFP_SYNC_ME;
 
    /* Index buffers use L2 since GFX8 */
    if (flags & PIPE_BARRIER_INDEX_BUFFER &&
        (sctx->gfx_level <= GFX7 || sctx->screen->info.cp_sdma_ge_use_system_memory_scope))
-      sctx->flags |= SI_CONTEXT_WB_L2;
+      sctx->barrier_flags |= SI_CONTEXT_WB_L2;
 
    /* Indirect buffers use L2 since GFX9. */
    if (flags & PIPE_BARRIER_INDIRECT_BUFFER &&
        (sctx->gfx_level <= GFX8 || sctx->screen->info.cp_sdma_ge_use_system_memory_scope))
-      sctx->flags |= SI_CONTEXT_WB_L2;
+      sctx->barrier_flags |= SI_CONTEXT_WB_L2;
 
    /* MSAA color images are flushed in si_decompress_textures when needed.
     * Shaders never write to depth/stencil images.
     */
    if (flags & PIPE_BARRIER_FRAMEBUFFER && sctx->framebuffer.uncompressed_cb_mask) {
-      sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
+      sctx->barrier_flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
 
       if (sctx->gfx_level >= GFX10 && sctx->gfx_level < GFX12) {
          if (sctx->screen->info.tcc_rb_non_coherent)
-            sctx->flags |= SI_CONTEXT_INV_L2;
+            sctx->barrier_flags |= SI_CONTEXT_INV_L2;
          else /* We don't know which shaders do image stores with DCC: */
-            sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
+            sctx->barrier_flags |= SI_CONTEXT_INV_L2_METADATA;
       } else if (sctx->gfx_level == GFX9) {
          /* We have to invalidate L2 for MSAA and when DCC can have pipe_aligned=0. */
-         sctx->flags |= SI_CONTEXT_INV_L2;
+         sctx->barrier_flags |= SI_CONTEXT_INV_L2;
       } else if (sctx->gfx_level <= GFX8) {
          /* CB doesn't use L2 on GFX6-8.  */
-         sctx->flags |= SI_CONTEXT_WB_L2;
+         sctx->barrier_flags |= SI_CONTEXT_WB_L2;
       }
    }
 
diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c
index d3c6919d200..7d1ff1ba4f4 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -507,7 +507,7 @@ static void si_blit_decompress_color(struct si_context *sctx, struct si_texture
          /* Required before and after FMASK and DCC_DECOMPRESS. */
          if (custom_blend == sctx->custom_blend_fmask_decompress ||
              custom_blend == sctx->custom_blend_dcc_decompress) {
-            sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
+            sctx->barrier_flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
             si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
          }
 
@@ -517,7 +517,7 @@ static void si_blit_decompress_color(struct si_context *sctx, struct si_texture
 
          if (custom_blend == sctx->custom_blend_fmask_decompress ||
              custom_blend == sctx->custom_blend_dcc_decompress) {
-            sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
+            sctx->barrier_flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
             si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
          }
 
@@ -1070,7 +1070,7 @@ static void si_do_CB_resolve(struct si_context *sctx, const struct pipe_blit_inf
                              enum pipe_format format)
 {
    /* Required before and after CB_RESOLVE. */
-   sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
+   sctx->barrier_flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
    si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
 
    si_blitter_begin(
diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c
index 7caccbcc85a..b978301fb2d 100644
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -67,11 +67,11 @@ void si_execute_clears(struct si_context *sctx, struct si_clear_info *info,
    }
 
    /* Invalidate the VMEM cache because we always use compute. */
-   sctx->flags |= SI_CONTEXT_INV_VCACHE;
+   sctx->barrier_flags |= SI_CONTEXT_INV_VCACHE;
 
    /* GFX6-8: CB and DB don't use L2. */
    if (sctx->gfx_level <= GFX8)
-      sctx->flags |= SI_CONTEXT_INV_L2;
+      sctx->barrier_flags |= SI_CONTEXT_INV_L2;
 
    si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
 
@@ -104,11 +104,11 @@ void si_execute_clears(struct si_context *sctx, struct si_clear_info *info,
    }
 
    /* Wait for idle. */
-   sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
+   sctx->barrier_flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
 
    /* GFX6-8: CB and DB don't use L2. */
    if (sctx->gfx_level <= GFX8)
-      sctx->flags |= SI_CONTEXT_WB_L2;
+      sctx->barrier_flags |= SI_CONTEXT_WB_L2;
 
    si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
 }
@@ -1209,7 +1209,7 @@ static void gfx6_clear(struct pipe_context *ctx, unsigned buffers,
             if ((zstex->depth_clear_value[level] != 0) != (depth != 0)) {
                /* ZRANGE_PRECISION register of a bound surface will change so we
                 * must flush the DB caches. */
-               sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB;
+               sctx->barrier_flags |= SI_CONTEXT_FLUSH_AND_INV_DB;
                si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
             }
             /* Update DB_DEPTH_CLEAR. */
@@ -1245,7 +1245,7 @@ static void gfx6_clear(struct pipe_context *ctx, unsigned buffers,
        * The root cause is unknown.
        */
       if (sctx->gfx_level == GFX11 || sctx->gfx_level == GFX11_5) {
-         sctx->flags |= SI_CONTEXT_VS_PARTIAL_FLUSH;
+         sctx->barrier_flags |= SI_CONTEXT_VS_PARTIAL_FLUSH;
          si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
       }
    }
diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c
index bd45c9ae96b..5544862dce9 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -1175,7 +1175,7 @@ static void si_launch_grid(struct pipe_context *ctx, const struct pipe_grid_info
                            info->block[0] * info->block[1] * info->block[2] > 256;
 
    if (cs_regalloc_hang) {
-      sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_CS_PARTIAL_FLUSH;
+      sctx->barrier_flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_CS_PARTIAL_FLUSH;
       si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
    }
 
@@ -1215,7 +1215,7 @@ static void si_launch_grid(struct pipe_context *ctx, const struct pipe_grid_info
       /* Indirect buffers are read through L2 on GFX9-GFX11, but not other hw. */
       if ((sctx->gfx_level <= GFX8 || sctx->gfx_level == GFX12) &&
           si_resource(info->indirect)->L2_cache_dirty) {
-         sctx->flags |= SI_CONTEXT_WB_L2 | SI_CONTEXT_PFP_SYNC_ME;
+         sctx->barrier_flags |= SI_CONTEXT_WB_L2 | SI_CONTEXT_PFP_SYNC_ME;
          si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
          si_resource(info->indirect)->L2_cache_dirty = false;
       }
@@ -1310,7 +1310,7 @@ static void si_launch_grid(struct pipe_context *ctx, const struct pipe_grid_info
       trace_si_end_compute(&sctx->trace, info->grid[0], info->grid[1], info->grid[2]);
 
    if (cs_regalloc_hang) {
-      sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
+      sctx->barrier_flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
       si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
    }
 }
diff --git a/src/gallium/drivers/radeonsi/si_compute_blit.c b/src/gallium/drivers/radeonsi/si_compute_blit.c
index 7019b4e20ab..ba1e9ec9640 100644
--- a/src/gallium/drivers/radeonsi/si_compute_blit.c
+++ b/src/gallium/drivers/radeonsi/si_compute_blit.c
@@ -14,9 +14,9 @@
 
 static void si_compute_begin_internal(struct si_context *sctx, bool render_condition_enabled)
 {
-   sctx->flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
+   sctx->barrier_flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
    if (sctx->num_hw_pipestat_streamout_queries) {
-      sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
+      sctx->barrier_flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
       si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
    }
 
@@ -32,9 +32,9 @@ static void si_compute_begin_internal(struct si_context *sctx, bool render_condi
 
 static void si_compute_end_internal(struct si_context *sctx)
 {
-   sctx->flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
+   sctx->barrier_flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
    if (sctx->num_hw_pipestat_streamout_queries) {
-      sctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
+      sctx->barrier_flags |= SI_CONTEXT_START_PIPELINE_STATS;
       si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
    }
 
@@ -345,7 +345,7 @@ void si_retile_dcc(struct si_context *sctx, struct si_texture *tex)
    assert(sctx->gfx_level < GFX12);
 
    /* Flush and wait for CB before retiling DCC. */
-   sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
+   sctx->barrier_flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
    si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
 
    /* Set the DCC buffer. */
diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/gallium/drivers/radeonsi/si_cp_dma.c
index 1f1e8eb8059..2ec13909727 100644
--- a/src/gallium/drivers/radeonsi/si_cp_dma.c
+++ b/src/gallium/drivers/radeonsi/si_cp_dma.c
@@ -151,7 +151,7 @@ void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
    assert(size && size % 4 == 0);
 
    if (!cp_dma_use_L2(sctx)) {
-      sctx->flags |= SI_CONTEXT_INV_L2;
+      sctx->barrier_flags |= SI_CONTEXT_INV_L2;
       si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
    }
 
@@ -234,7 +234,7 @@ void si_cp_dma_copy_buffer(struct si_context *sctx, struct pipe_resource *dst,
    assert(dst && src);
 
    if (!cp_dma_use_L2(sctx)) {
-      sctx->flags |= SI_CONTEXT_INV_L2;
+      sctx->barrier_flags |= SI_CONTEXT_INV_L2;
       si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
    }
 
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 676e3f159ae..d3783e910d4 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -1897,7 +1897,7 @@ static void si_upload_bindless_descriptors(struct si_context *sctx)
    /* Wait for graphics/compute to be idle before updating the resident
     * descriptors directly in memory, in case the GPU is using them.
     */
-   sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_CS_PARTIAL_FLUSH;
+   sctx->barrier_flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_CS_PARTIAL_FLUSH;
    si_emit_barrier_direct(sctx);
 
    util_dynarray_foreach (&sctx->resident_tex_handles, struct si_texture_handle *, tex_handle) {
@@ -1921,11 +1921,11 @@ static void si_upload_bindless_descriptors(struct si_context *sctx)
    }
 
    /* Invalidate scalar L0 because the cache doesn't know that L2 changed. */
-   sctx->flags |= SI_CONTEXT_INV_SCACHE;
+   sctx->barrier_flags |= SI_CONTEXT_INV_SCACHE;
 
    /* TODO: Range-invalidate GL2 */
    if (sctx->screen->info.cp_sdma_ge_use_system_memory_scope)
-      sctx->flags |= SI_CONTEXT_INV_L2;
+      sctx->barrier_flags |= SI_CONTEXT_INV_L2;
 
    sctx->bindless_descriptors_dirty = false;
 }
diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c
index 28d29e46088..ab0693ebe7a 100644
--- a/src/gallium/drivers/radeonsi/si_gfx_cs.c
+++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c
@@ -166,7 +166,7 @@ void si_flush_gfx_cs(struct si_context *ctx, unsigned flags, struct pipe_fence_h
 
    /* Wait for draw calls to finish if needed. */
    if (wait_flags) {
-      ctx->flags |= wait_flags;
+      ctx->barrier_flags |= wait_flags;
       si_emit_barrier_direct(ctx);
    }
    ctx->gfx_last_ib_is_busy = (wait_flags & wait_ps_cs) != wait_ps_cs;
@@ -462,16 +462,16 @@ void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs)
     *
     * TODO: Do we also need to invalidate CB & DB caches?
     */
-   ctx->flags |= SI_CONTEXT_INV_L2;
+   ctx->barrier_flags |= SI_CONTEXT_INV_L2;
    if (ctx->gfx_level < GFX10)
-      ctx->flags |= SI_CONTEXT_INV_ICACHE | SI_CONTEXT_INV_SCACHE | SI_CONTEXT_INV_VCACHE;
+      ctx->barrier_flags |= SI_CONTEXT_INV_ICACHE | SI_CONTEXT_INV_SCACHE | SI_CONTEXT_INV_VCACHE;
 
    /* Disable pipeline stats if there are no active queries. */
-   ctx->flags &= ~SI_CONTEXT_START_PIPELINE_STATS & ~SI_CONTEXT_STOP_PIPELINE_STATS;
+   ctx->barrier_flags &= ~SI_CONTEXT_START_PIPELINE_STATS & ~SI_CONTEXT_STOP_PIPELINE_STATS;
    if (ctx->num_hw_pipestat_streamout_queries)
-      ctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
+      ctx->barrier_flags |= SI_CONTEXT_START_PIPELINE_STATS;
    else
-      ctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
+      ctx->barrier_flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
 
    ctx->pipeline_stats_enabled = -1; /* indicate that the current hw state is unknown */
 
@@ -479,7 +479,7 @@ void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs)
     * When switching NGG->legacy, we need to flush VGT for certain hw generations.
     */
    if (ctx->screen->info.has_vgt_flush_ngg_legacy_bug && !ctx->ngg)
-      ctx->flags |= SI_CONTEXT_VGT_FLUSH;
+      ctx->barrier_flags |= SI_CONTEXT_VGT_FLUSH;
 
    si_mark_atom_dirty(ctx, &ctx->atoms.s.barrier);
    si_mark_atom_dirty(ctx, &ctx->atoms.s.spi_ge_ring_state);
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 0b30d19495a..6a8e057058e 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -1007,7 +1007,7 @@ struct si_context {
       unsigned with_cb;
       unsigned with_db;
    } num_draw_calls_sh_coherent;
-   unsigned flags; /* flush flags */
+   unsigned barrier_flags;
 
    /* Atoms (state emit functions). */
    union si_state_atoms atoms;
@@ -1875,26 +1875,26 @@ static inline void si_saved_cs_reference(struct si_saved_cs **dst, struct si_sav
 static inline void si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
                                               bool shaders_read_metadata, bool dcc_pipe_aligned)
 {
-   sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_INV_VCACHE;
+   sctx->barrier_flags |= SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_INV_VCACHE;
    sctx->force_shader_coherency.with_cb = false;
 
    if (sctx->gfx_level >= GFX10 && sctx->gfx_level < GFX12) {
       if (sctx->screen->info.tcc_rb_non_coherent)
-         sctx->flags |= SI_CONTEXT_INV_L2;
+         sctx->barrier_flags |= SI_CONTEXT_INV_L2;
       else if (shaders_read_metadata)
-         sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
+         sctx->barrier_flags |= SI_CONTEXT_INV_L2_METADATA;
    } else if (sctx->gfx_level == GFX9) {
       /* Single-sample color is coherent with shaders on GFX9, but
        * L2 metadata must be flushed if shaders read metadata.
        * (DCC, CMASK).
        */
       if (num_samples >= 2 || (shaders_read_metadata && !dcc_pipe_aligned))
-         sctx->flags |= SI_CONTEXT_INV_L2;
+         sctx->barrier_flags |= SI_CONTEXT_INV_L2;
       else if (shaders_read_metadata)
-         sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
+         sctx->barrier_flags |= SI_CONTEXT_INV_L2_METADATA;
    } else if (sctx->gfx_level <= GFX8) {
       /* GFX6-GFX8 */
-      sctx->flags |= SI_CONTEXT_INV_L2;
+      sctx->barrier_flags |= SI_CONTEXT_INV_L2;
    }
 
    si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
@@ -1903,26 +1903,26 @@ static inline void si_make_CB_shader_coherent(struct si_context *sctx, unsigned
 static inline void si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
                                               bool include_stencil, bool shaders_read_metadata)
 {
-   sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB | SI_CONTEXT_INV_VCACHE;
+   sctx->barrier_flags |= SI_CONTEXT_FLUSH_AND_INV_DB | SI_CONTEXT_INV_VCACHE;
    sctx->force_shader_coherency.with_db = false;
 
    if (sctx->gfx_level >= GFX10 && sctx->gfx_level < GFX12) {
       if (sctx->screen->info.tcc_rb_non_coherent)
-         sctx->flags |= SI_CONTEXT_INV_L2;
+         sctx->barrier_flags |= SI_CONTEXT_INV_L2;
       else if (shaders_read_metadata)
-         sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
+         sctx->barrier_flags |= SI_CONTEXT_INV_L2_METADATA;
    } else if (sctx->gfx_level == GFX9) {
       /* Single-sample depth (not stencil) is coherent with shaders
        * on GFX9, but L2 metadata must be flushed if shaders read
        * metadata.
        */
       if (num_samples >= 2 || include_stencil)
-         sctx->flags |= SI_CONTEXT_INV_L2;
+         sctx->barrier_flags |= SI_CONTEXT_INV_L2;
       else if (shaders_read_metadata)
-         sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
+         sctx->barrier_flags |= SI_CONTEXT_INV_L2_METADATA;
    } else if (sctx->gfx_level <= GFX8) {
       /* GFX6-GFX8 */
-      sctx->flags |= SI_CONTEXT_INV_L2;
+      sctx->barrier_flags |= SI_CONTEXT_INV_L2;
    }
 
    si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
@@ -2210,7 +2210,7 @@ si_set_rasterized_prim(struct si_context *sctx, enum mesa_prim rast_prim,
  */
 static inline void si_emit_barrier_direct(struct si_context *sctx)
 {
-   if (sctx->flags) {
+   if (sctx->barrier_flags) {
       sctx->emit_barrier(sctx, &sctx->gfx_cs);
       sctx->dirty_atoms &= ~SI_ATOM_BIT(barrier);
    }
diff --git a/src/gallium/drivers/radeonsi/si_query.c b/src/gallium/drivers/radeonsi/si_query.c
index 1932bda7a60..19c0a2f996c 100644
--- a/src/gallium/drivers/radeonsi/si_query.c
+++ b/src/gallium/drivers/radeonsi/si_query.c
@@ -888,12 +888,12 @@ static void si_update_hw_pipeline_stats(struct si_context *sctx, unsigned type,
 
       /* Enable/disable pipeline stats if we have any queries. */
       if (diff == 1 && sctx->num_hw_pipestat_streamout_queries == 1) {
-         sctx->flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
-         sctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
+         sctx->barrier_flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
+         sctx->barrier_flags |= SI_CONTEXT_START_PIPELINE_STATS;
          si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
       } else if (diff == -1 && sctx->num_hw_pipestat_streamout_queries == 0) {
-         sctx->flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
-         sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
+         sctx->barrier_flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
+         sctx->barrier_flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
          si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
       }
    }
@@ -1599,8 +1599,8 @@ static void si_query_hw_get_result_resource(struct si_context *sctx, struct si_q
       break;
    }
 
-   sctx->flags |= SI_CONTEXT_INV_SCACHE | SI_CONTEXT_INV_VCACHE |
-                  (sctx->gfx_level <= GFX8 ? SI_CONTEXT_INV_L2 : 0);
+   sctx->barrier_flags |= SI_CONTEXT_INV_SCACHE | SI_CONTEXT_INV_VCACHE |
+                          (sctx->gfx_level <= GFX8 ? SI_CONTEXT_INV_L2 : 0);
    si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
 
    for (qbuf = &query->buffer; qbuf; qbuf = qbuf_prev) {
@@ -1698,7 +1698,7 @@ static void si_render_condition(struct pipe_context *ctx, struct pipe_query *que
          /* Settings this in the render cond atom is too late,
           * so set it here. */
          if (sctx->gfx_level <= GFX8) {
-            sctx->flags |= SI_CONTEXT_WB_L2 | SI_CONTEXT_PFP_SYNC_ME;
+            sctx->barrier_flags |= SI_CONTEXT_WB_L2 | SI_CONTEXT_PFP_SYNC_ME;
             si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
          }
 
diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index ee3eab3ea12..ed3ee31dbe5 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -988,7 +988,7 @@ static void post_upload_binary(struct si_screen *sscreen, struct si_shader *shad
       si_cp_dma_copy_buffer(upload_ctx, &shader->bo->b.b, staging, 0, staging_offset,
                             binary_size);
       si_barrier_after_simple_buffer_op(upload_ctx, 0, &shader->bo->b.b, staging);
-      upload_ctx->flags |= SI_CONTEXT_INV_ICACHE | SI_CONTEXT_INV_L2;
+      upload_ctx->barrier_flags |= SI_CONTEXT_INV_ICACHE | SI_CONTEXT_INV_L2;
 
 #if 0 /* debug: validate whether the copy was successful */
       uint32_t *dst_binary = malloc(binary_size);
diff --git a/src/gallium/drivers/radeonsi/si_sqtt.c b/src/gallium/drivers/radeonsi/si_sqtt.c
index 9b82755eb8a..57181e287b6 100644
--- a/src/gallium/drivers/radeonsi/si_sqtt.c
+++ b/src/gallium/drivers/radeonsi/si_sqtt.c
@@ -93,8 +93,8 @@ static void si_emit_sqtt_stop(struct si_context *sctx, struct radeon_cmdbuf *cs,
    if (sctx->screen->info.has_sqtt_rb_harvest_bug) {
       /* Some chips with disabled RBs should wait for idle because FINISH_DONE
        * doesn't work. */
-      sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB |
-                     SI_CONTEXT_CS_PARTIAL_FLUSH;
+      sctx->barrier_flags |= SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB |
+                             SI_CONTEXT_CS_PARTIAL_FLUSH;
       sctx->emit_barrier(sctx, cs);
    }
 
@@ -140,10 +140,10 @@ static void si_sqtt_start(struct si_context *sctx, struct radeon_cmdbuf *cs)
    si_cp_dma_wait_for_idle(sctx, cs);
 
    /* Make sure to wait-for-idle before starting SQTT. */
-   sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_CS_PARTIAL_FLUSH |
-                  SI_CONTEXT_INV_ICACHE | SI_CONTEXT_INV_SCACHE |
-                  SI_CONTEXT_INV_VCACHE | SI_CONTEXT_INV_L2 |
-                  SI_CONTEXT_PFP_SYNC_ME;
+   sctx->barrier_flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_CS_PARTIAL_FLUSH |
+                          SI_CONTEXT_INV_ICACHE | SI_CONTEXT_INV_SCACHE |
+                          SI_CONTEXT_INV_VCACHE | SI_CONTEXT_INV_L2 |
+                          SI_CONTEXT_PFP_SYNC_ME;
    sctx->emit_barrier(sctx, cs);
 
    si_inhibit_clockgating(sctx, cs, true);
@@ -200,10 +200,10 @@ static void si_sqtt_stop(struct si_context *sctx, struct radeon_cmdbuf *cs)
                           sctx->screen->info.never_send_perfcounter_stop);
 
    /* Make sure to wait-for-idle before stopping SQTT. */
-   sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_CS_PARTIAL_FLUSH |
-                  SI_CONTEXT_INV_ICACHE | SI_CONTEXT_INV_SCACHE |
-                  SI_CONTEXT_INV_VCACHE | SI_CONTEXT_INV_L2 |
-                  SI_CONTEXT_PFP_SYNC_ME;
+   sctx->barrier_flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_CS_PARTIAL_FLUSH |
+                          SI_CONTEXT_INV_ICACHE | SI_CONTEXT_INV_SCACHE |
+                          SI_CONTEXT_INV_VCACHE | SI_CONTEXT_INV_L2 |
+                          SI_CONTEXT_PFP_SYNC_ME;
    sctx->emit_barrier(sctx, cs);
 
    si_emit_sqtt_stop(sctx, cs, ip_type);
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index cc5d98134a8..0eaadb53f65 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1756,14 +1756,14 @@ static void si_set_active_query_state(struct pipe_context *ctx, bool enable)
    if (enable) {
       /* Disable pipeline stats if there are no active queries. */
       if (sctx->num_hw_pipestat_streamout_queries) {
-         sctx->flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
-         sctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
+         sctx->barrier_flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
+         sctx->barrier_flags |= SI_CONTEXT_START_PIPELINE_STATS;
          si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
       }
    } else {
       if (sctx->num_hw_pipestat_streamout_queries) {
-         sctx->flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
-         sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
+         sctx->barrier_flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
+         sctx->barrier_flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
          si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
       }
    }
@@ -2632,7 +2632,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
    /* Wait for CS because: shader write -> FB read
     * Wait for PS because: texture -> render (eg: glBlitFramebuffer(with src=dst) then glDraw*)
     */
-   sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH | SI_CONTEXT_PS_PARTIAL_FLUSH;
+   sctx->barrier_flags |= SI_CONTEXT_CS_PARTIAL_FLUSH | SI_CONTEXT_PS_PARTIAL_FLUSH;
    si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
 
    /* DB caches are flushed on demand (using si_decompress_textures) except the cases below. */
@@ -2660,7 +2660,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
           *
           * This seems to fix them:
           */
-         sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB | SI_CONTEXT_INV_L2;
+         sctx->barrier_flags |= SI_CONTEXT_FLUSH_AND_INV_DB | SI_CONTEXT_INV_L2;
          si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
       }
    } else if (sctx->gfx_level == GFX9) {
@@ -2670,7 +2670,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
        *  - render with DEPTH_BEFORE_SHADER=1
        * Flushing DB metadata works around the problem.
        */
-      sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
+      sctx->barrier_flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
       si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
    }
 
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.cpp b/src/gallium/drivers/radeonsi/si_state_draw.cpp
index 21ca8403b8e..3c83adc8e55 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.cpp
+++ b/src/gallium/drivers/radeonsi/si_state_draw.cpp
@@ -906,8 +906,8 @@ static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
           num_instanced_prims_less_than<IS_DRAW_VERTEX_STATE>(indirect, prim, min_vertex_count,
                                                               instance_count, 2, sctx->patch_vertices)) {
          /* The cache flushes should have been emitted already. */
-         assert(sctx->flags == 0);
-         sctx->flags = SI_CONTEXT_VGT_FLUSH;
+         assert(sctx->barrier_flags == 0);
+         sctx->barrier_flags = SI_CONTEXT_VGT_FLUSH;
          si_emit_barrier_direct(sctx);
       }
    }
@@ -2121,7 +2121,7 @@ static void si_draw(struct pipe_context *ctx,
          index_size = 2;
 
          /* GFX6-7 don't read index buffers through L2. */
-         sctx->flags |= SI_CONTEXT_WB_L2 | SI_CONTEXT_PFP_SYNC_ME;
+         sctx->barrier_flags |= SI_CONTEXT_WB_L2 | SI_CONTEXT_PFP_SYNC_ME;
          si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
          si_resource(indexbuf)->L2_cache_dirty = false;
       } else if (!IS_DRAW_VERTEX_STATE && info->has_user_indices) {
@@ -2144,7 +2144,7 @@ static void si_draw(struct pipe_context *ctx,
                  si_resource(indexbuf)->L2_cache_dirty) {
          /* GFX8-GFX11 reads index buffers through L2, so it doesn't
           * need this. */
-         sctx->flags |= SI_CONTEXT_WB_L2 | SI_CONTEXT_PFP_SYNC_ME;
+         sctx->barrier_flags |= SI_CONTEXT_WB_L2 | SI_CONTEXT_PFP_SYNC_ME;
          si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
          si_resource(indexbuf)->L2_cache_dirty = false;
       }
@@ -2157,14 +2157,14 @@ static void si_draw(struct pipe_context *ctx,
       /* Indirect buffers use L2 on GFX9-GFX11, but not other hw. */
       if (GFX_VERSION <= GFX8 || GFX_VERSION == GFX12) {
          if (indirect->buffer && si_resource(indirect->buffer)->L2_cache_dirty) {
-            sctx->flags |= SI_CONTEXT_WB_L2 | SI_CONTEXT_PFP_SYNC_ME;
+            sctx->barrier_flags |= SI_CONTEXT_WB_L2 | SI_CONTEXT_PFP_SYNC_ME;
             si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
             si_resource(indirect->buffer)->L2_cache_dirty = false;
          }
 
          if (indirect->indirect_draw_count &&
              si_resource(indirect->indirect_draw_count)->L2_cache_dirty) {
-            sctx->flags |= SI_CONTEXT_WB_L2 | SI_CONTEXT_PFP_SYNC_ME;
+            sctx->barrier_flags |= SI_CONTEXT_WB_L2 | SI_CONTEXT_PFP_SYNC_ME;
             si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
             si_resource(indirect->indirect_draw_count)->L2_cache_dirty = false;
          }
@@ -2302,7 +2302,7 @@ static void si_draw(struct pipe_context *ctx,
    si_emit_rasterizer_prim_state<GFX_VERSION, HAS_GS, NGG>(sctx);
    /* This emits states and flushes caches. */
    si_emit_all_states(sctx, masked_atoms);
-   /* This can be done after si_emit_all_states because it doesn't set cache flush flags. */
+   /* This can be done after si_emit_all_states because it doesn't set barrier flags. */
    si_emit_draw_registers<GFX_VERSION, HAS_TESS, HAS_GS, NGG, IS_DRAW_VERTEX_STATE>
          (sctx, indirect, prim, index_size, instance_count, primitive_restart,
           info->restart_index, min_direct_count);
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.cpp b/src/gallium/drivers/radeonsi/si_state_shaders.cpp
index 952a956dc19..1cd3bdf0b03 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.cpp
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.cpp
@@ -3769,7 +3769,7 @@ bool si_update_ngg(struct si_context *sctx)
        * pointers are set.
        */
       if (sctx->screen->info.has_vgt_flush_ngg_legacy_bug && !new_ngg) {
-         sctx->flags |= SI_CONTEXT_VGT_FLUSH;
+         sctx->barrier_flags |= SI_CONTEXT_VGT_FLUSH;
          si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
 
          if (sctx->gfx_level == GFX10) {
diff --git a/src/gallium/drivers/radeonsi/si_state_streamout.c b/src/gallium/drivers/radeonsi/si_state_streamout.c
index a1e69ff4cea..fa58d371f0e 100644
--- a/src/gallium/drivers/radeonsi/si_state_streamout.c
+++ b/src/gallium/drivers/radeonsi/si_state_streamout.c
@@ -98,12 +98,12 @@ static void si_set_streamout_targets(struct pipe_context *ctx, unsigned num_targ
        * VS_PARTIAL_FLUSH is required if the buffers are going to be
        * used as an input immediately.
        */
-      sctx->flags |= SI_CONTEXT_INV_SCACHE | SI_CONTEXT_INV_VCACHE |
-                     SI_CONTEXT_VS_PARTIAL_FLUSH | SI_CONTEXT_PFP_SYNC_ME;
+      sctx->barrier_flags |= SI_CONTEXT_INV_SCACHE | SI_CONTEXT_INV_VCACHE |
+                             SI_CONTEXT_VS_PARTIAL_FLUSH | SI_CONTEXT_PFP_SYNC_ME;
 
       /* Make the streamout state buffer available to the CP for resuming and DrawTF. */
       if (sctx->screen->info.cp_sdma_ge_use_system_memory_scope)
-         sctx->flags |= SI_CONTEXT_WB_L2;
+         sctx->barrier_flags |= SI_CONTEXT_WB_L2;
 
       si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
    }
@@ -227,8 +227,8 @@ static void si_set_streamout_targets(struct pipe_context *ctx, unsigned num_targ
       /* All readers of the streamout targets need to be finished before we can
        * start writing to them.
        */
-      sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_CS_PARTIAL_FLUSH |
-                     SI_CONTEXT_PFP_SYNC_ME;
+      sctx->barrier_flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_CS_PARTIAL_FLUSH |
+                             SI_CONTEXT_PFP_SYNC_ME;
       si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
    } else {
       si_set_atom_dirty(sctx, &sctx->atoms.s.streamout_begin, false);
@@ -371,7 +371,7 @@ void si_emit_streamout_end(struct si_context *sctx)
 
    if (sctx->gfx_level >= GFX11) {
       /* Wait for streamout to finish before reading GDS_STRMOUT registers. */
-      sctx->flags |= SI_CONTEXT_VS_PARTIAL_FLUSH;
+      sctx->barrier_flags |= SI_CONTEXT_VS_PARTIAL_FLUSH;
       si_emit_barrier_direct(sctx);
    } else {
       si_flush_vgt_streamout(sctx);
@@ -387,7 +387,7 @@ void si_emit_streamout_end(struct si_context *sctx)
                          COPY_DATA_REG, NULL,
                          (R_031088_GDS_STRMOUT_DWORDS_WRITTEN_0 >> 2) + i);
          /* For DrawTF reading buf_filled_size: */
-         sctx->flags |= SI_CONTEXT_PFP_SYNC_ME;
+         sctx->barrier_flags |= SI_CONTEXT_PFP_SYNC_ME;
          si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
       } else {
          uint64_t va = t[i]->buf_filled_size->gpu_address + t[i]->buf_filled_size_offset;
diff --git a/src/gallium/drivers/radeonsi/si_test_blit_perf.c b/src/gallium/drivers/radeonsi/si_test_blit_perf.c
index d215d4c1340..9cc84e45e3b 100644
--- a/src/gallium/drivers/radeonsi/si_test_blit_perf.c
+++ b/src/gallium/drivers/radeonsi/si_test_blit_perf.c
@@ -537,7 +537,7 @@ void si_test_blit_perf(struct si_screen *sscreen)
                                     case METHOD_DEFAULT:
                                        if (test_flavor == TEST_FB_CLEAR) {
                                           ctx->clear(ctx, PIPE_CLEAR_COLOR, NULL, clear_color, 0, 0);
-                                          sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_INV_L2;
+                                          sctx->barrier_flags |= SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_INV_L2;
                                        } else {
                                           ctx->clear_render_target(ctx, dst_surf, clear_color,
                                                                    dst_box.x, dst_box.y,
@@ -640,10 +640,10 @@ void si_test_blit_perf(struct si_screen *sscreen)
                               }
 
                               /* Wait for idle after all tests. */
-                              sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
-                                             SI_CONTEXT_CS_PARTIAL_FLUSH |
-                                             SI_CONTEXT_INV_L2 | SI_CONTEXT_INV_SCACHE |
-                                             SI_CONTEXT_INV_VCACHE;
+                              sctx->barrier_flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
+                                                     SI_CONTEXT_CS_PARTIAL_FLUSH |
+                                                     SI_CONTEXT_INV_L2 | SI_CONTEXT_INV_SCACHE |
+                                                     SI_CONTEXT_INV_VCACHE;
                               si_emit_barrier_direct(sctx);
 
                               ctx->end_query(ctx, q);
diff --git a/src/gallium/drivers/radeonsi/si_test_dma_perf.c b/src/gallium/drivers/radeonsi/si_test_dma_perf.c
index 24295168a3b..71481bb96ee 100644
--- a/src/gallium/drivers/radeonsi/si_test_dma_perf.c
+++ b/src/gallium/drivers/radeonsi/si_test_dma_perf.c
@@ -257,7 +257,7 @@ void si_test_dma_perf(struct si_screen *sscreen)
                      si_barrier_after_simple_buffer_op(sctx, 0, dst, src);
                   }
 
-                  sctx->flags |= SI_CONTEXT_INV_L2;
+                  sctx->barrier_flags |= SI_CONTEXT_INV_L2;
                }
 
                ctx->end_query(ctx, q);