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docs/isl: fix typos & formatting

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Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17522>
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Eric Engestrom
2022-07-13 18:53:22 +01:00
committed by Marge Bot
parent 648731e2bd
commit 8317de8ed3
3 changed files with 6 additions and 6 deletions
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docs/isl/ccs.rst
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@@ -52,7 +52,7 @@ concerned, is that fast-clears use only 1 bit per cache-line pair whereas color
compression uses 2 bits.
What is a cache-line pair? Both the X and Y tiling formats are arranged as an
8x8 grid of cache lines. (See the [chapter on tiling](#tiling) for more
8x8 grid of cache lines. (See the :doc:`chapter on tiling <tiling>` for more
details.) In either case, a cache-line pair is a pair of cache lines whose
starting addresses differ by 512 bytes or 8 cache lines. This results in the
two cache lines being vertically adjacent when the main surface is X-tiled and