From 82283de717aef6575385a9e3c17b59433c00bf91 Mon Sep 17 00:00:00 2001 From: Konstantin Seurer Date: Thu, 30 Jun 2022 16:27:05 +0200 Subject: [PATCH] radv: Use a global address for sbt_base Required for indirect(2) ray tracing to work. Fixes the following tests: dEQP-VK.ray_tracing_pipeline.trace_rays_indirect2.indirect_* dEQP-VK.ray_tracing_pipeline.trace_rays_cmds_maintenance_1.indirect2_* Fixes: 16585664 ("radv: vkCmdTraceRaysIndirect2KHR") Signed-off-by: Konstantin Seurer Reviewed-by: Samuel Pitoiset Part-of: --- src/amd/compiler/aco_instruction_selection.cpp | 3 ++- src/amd/vulkan/radv_cmd_buffer.c | 2 +- src/amd/vulkan/radv_shader_args.c | 6 +++--- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 697ec2db765..22536dc267f 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -9169,7 +9169,8 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) } case nir_intrinsic_load_sbt_base_amd: { Temp dst = get_ssa_temp(ctx, &instr->dest.ssa); - Temp addr = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->ac.sbt_descriptors)); + Temp addr = get_arg(ctx, ctx->args->ac.sbt_descriptors); + assert(addr.regClass() == s2); bld.copy(Definition(dst), Operand(addr)); break; } diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index f51aba184da..5ea72baa114 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -7794,7 +7794,7 @@ radv_trace_rays(struct radv_cmd_buffer *cmd_buffer, const VkTraceRaysIndirectCom radv_lookup_user_sgpr(&pipeline->base, MESA_SHADER_COMPUTE, AC_UD_CS_SBT_DESCRIPTORS); if (desc_loc->sgpr_idx != -1) { radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs, - base_reg + desc_loc->sgpr_idx * 4, sbt_va, false); + base_reg + desc_loc->sgpr_idx * 4, sbt_va, true); } struct radv_userdata_info *size_loc = diff --git a/src/amd/vulkan/radv_shader_args.c b/src/amd/vulkan/radv_shader_args.c index 9564899140e..e63013b9be9 100644 --- a/src/amd/vulkan/radv_shader_args.c +++ b/src/amd/vulkan/radv_shader_args.c @@ -51,7 +51,7 @@ static void set_loc_shader_ptr(struct radv_shader_args *args, int idx, uint8_t *sgpr_idx) { bool use_32bit_pointers = idx != AC_UD_SCRATCH_RING_OFFSETS && - idx != AC_UD_CS_TASK_RING_OFFSETS && + idx != AC_UD_CS_TASK_RING_OFFSETS && idx != AC_UD_CS_SBT_DESCRIPTORS && idx != AC_UD_CS_RAY_LAUNCH_SIZE_ADDR; set_loc_shader(args, idx, sgpr_idx, use_32bit_pointers ? 1 : 2); @@ -172,7 +172,7 @@ allocate_user_sgprs(enum amd_gfx_level gfx_level, const struct radv_shader_info case MESA_SHADER_COMPUTE: case MESA_SHADER_TASK: if (info->cs.uses_sbt) - user_sgpr_count += 1; + user_sgpr_count += 2; if (info->cs.uses_grid_size) user_sgpr_count += args->load_grid_size_from_user_sgpr ? 3 : 2; if (info->cs.uses_ray_launch_size) @@ -565,7 +565,7 @@ radv_declare_shader_args(enum amd_gfx_level gfx_level, const struct radv_pipelin declare_global_input_sgprs(info, &user_sgpr_info, args); if (info->cs.uses_sbt) { - ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_CONST_DESC_PTR, &args->ac.sbt_descriptors); + ac_add_arg(&args->ac, AC_ARG_SGPR, 2, AC_ARG_CONST_PTR, &args->ac.sbt_descriptors); } if (info->cs.uses_grid_size) {