From 820370ca087a619bbd961e822bec6db6cf03479c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Mon, 1 Apr 2024 01:11:36 +0200 Subject: [PATCH] radv: Change input patch size in TCS offchip layout to match RadeonSI. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Timur Kristóf Reviewed-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/nir/radv_nir_lower_abi.c | 3 ++- src/amd/vulkan/radv_cmd_buffer.c | 2 +- src/amd/vulkan/radv_shader.h | 4 ++-- src/amd/vulkan/radv_shader_args.h | 4 ++-- 4 files changed, 7 insertions(+), 6 deletions(-) diff --git a/src/amd/vulkan/nir/radv_nir_lower_abi.c b/src/amd/vulkan/nir/radv_nir_lower_abi.c index f68c8d80dfa..df1d5110c29 100644 --- a/src/amd/vulkan/nir/radv_nir_lower_abi.c +++ b/src/amd/vulkan/nir/radv_nir_lower_abi.c @@ -175,7 +175,8 @@ lower_abi_instr(nir_builder *b, nir_intrinsic_instr *intrin, void *state) if (s->gfx_state->ts.patch_control_points) { replacement = nir_imm_int(b, s->gfx_state->ts.patch_control_points); } else { - replacement = GET_SGPR_FIELD_NIR(s->args->tcs_offchip_layout, TCS_OFFCHIP_LAYOUT_PATCH_CONTROL_POINTS); + nir_def *n = GET_SGPR_FIELD_NIR(s->args->tcs_offchip_layout, TCS_OFFCHIP_LAYOUT_PATCH_CONTROL_POINTS); + replacement = nir_iadd_imm_nuw(b, n, 1); } } else if (stage == MESA_SHADER_TESS_EVAL) { if (s->info->tes.tcs_vertices_out) { diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index cf7fb42da81..5eab1f17d2a 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -2690,7 +2690,7 @@ radv_emit_patch_control_points(struct radv_cmd_buffer *cmd_buffer) assert(offchip->num_sgprs == 1); unsigned tcs_offchip_layout = - SET_SGPR_FIELD(TCS_OFFCHIP_LAYOUT_PATCH_CONTROL_POINTS, d->vk.ts.patch_control_points) | + SET_SGPR_FIELD(TCS_OFFCHIP_LAYOUT_PATCH_CONTROL_POINTS, d->vk.ts.patch_control_points - 1) | SET_SGPR_FIELD(TCS_OFFCHIP_LAYOUT_NUM_PATCHES, cmd_buffer->state.tess_num_patches) | SET_SGPR_FIELD(TCS_OFFCHIP_LAYOUT_NUM_LS_OUTPUTS, vs->info.vs.num_linked_outputs) | SET_SGPR_FIELD(TCS_OFFCHIP_LAYOUT_NUM_HS_OUTPUTS, tcs->info.tcs.num_linked_outputs) | diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index e4a6a0f2fbb..c92af7ad3d5 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -248,10 +248,10 @@ enum radv_ud_index { #define SET_SGPR_FIELD(field, value) (((unsigned)(value)&field##__MASK) << field##__SHIFT) -#define TCS_OFFCHIP_LAYOUT_PATCH_CONTROL_POINTS__SHIFT 0 -#define TCS_OFFCHIP_LAYOUT_PATCH_CONTROL_POINTS__MASK 0x3f #define TCS_OFFCHIP_LAYOUT_NUM_PATCHES__SHIFT 6 #define TCS_OFFCHIP_LAYOUT_NUM_PATCHES__MASK 0x3f +#define TCS_OFFCHIP_LAYOUT_PATCH_CONTROL_POINTS__SHIFT 12 +#define TCS_OFFCHIP_LAYOUT_PATCH_CONTROL_POINTS__MASK 0x1f #define TCS_OFFCHIP_LAYOUT_NUM_LS_OUTPUTS__SHIFT 17 #define TCS_OFFCHIP_LAYOUT_NUM_LS_OUTPUTS__MASK 0x3f #define TCS_OFFCHIP_LAYOUT_NUM_HS_OUTPUTS__SHIFT 23 diff --git a/src/amd/vulkan/radv_shader_args.h b/src/amd/vulkan/radv_shader_args.h index 7ab6bc04215..bc8e896b028 100644 --- a/src/amd/vulkan/radv_shader_args.h +++ b/src/amd/vulkan/radv_shader_args.h @@ -67,9 +67,9 @@ struct radv_shader_args { struct ac_arg sample_mask; /* TCS */ - /* # [0:5] = the number of patch control points + /* # [0:5] = reserved for future use * # [6:11] = the number of tessellation patches - * # [12:16] = reserved for future use + * # [12:16] = the number of input patch control points minus one, max = 31 * # [17:22] = the number of LS outputs, up to 32 * # [23:28] = the number of HS per-vertex outputs, up to 32 * # [29:30] = tess_primitive_mode