diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp
index 0f4568dff7c..cfb402b30dc 100644
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -12476,6 +12476,7 @@ select_trap_handler_shader(Program* program, struct nir_shader* shader, ac_shade
       5, /* WH_REG_GPR_ALLOC */
       7, /* HW_REG_IB_STS */
    };
+   uint32_t offset = 8;
 
    /* Store some hardware registers. */
    for (unsigned i = 0; i < ARRAY_SIZE(hw_regs_idx); i++) {
@@ -12487,14 +12488,28 @@ select_trap_handler_shader(Program* program, struct nir_shader* shader, ac_shade
          bld.copy(Definition(PhysReg{256}, v1) /* v0 */, Operand(PhysReg{ttmp8}, s1));
 
          bld.mubuf(aco_opcode::buffer_store_dword, Operand(PhysReg{ttmp4}, s4), Operand(v1),
-                   Operand::c32(8u + i * 4), Operand(PhysReg{256}, v1) /* v0 */, 0 /* offset */,
+                   Operand::c32(offset), Operand(PhysReg{256}, v1) /* v0 */, 0 /* offset */,
                    false /* offen */, false /* idxen */, /* addr64 */ false,
                    /* disable_wqm */ false, cache_glc);
       } else {
          bld.smem(aco_opcode::s_buffer_store_dword, Operand(PhysReg{ttmp4}, s4),
-                  Operand::c32(8u + i * 4), Operand(PhysReg{ttmp8}, s1), memory_sync_info(),
-                  cache_glc);
+                  Operand::c32(offset), Operand(PhysReg{ttmp8}, s1), memory_sync_info(), cache_glc);
       }
+
+      offset += 4;
+   }
+
+   /* Dump all SGPRs. */
+   for (uint32_t i = 0; i < program->dev.sgpr_limit; i++) {
+      bld.copy(Definition(PhysReg{256}, v1) /* v0 */, Operand(PhysReg{i}, s1));
+      bld.copy(Definition(PhysReg{ttmp8}, s1), Operand::c32(offset));
+
+      bld.mubuf(aco_opcode::buffer_store_dword, Operand(PhysReg{ttmp4}, s4), Operand(v1),
+                Operand(PhysReg{ttmp8}, s1), Operand(PhysReg{256}, v1) /* v0 */, 0 /* offset */,
+                false /* offen */, false /* idxen */, /* addr64 */ false,
+                /* disable_wqm */ false, cache_glc);
+
+      offset += 4;
    }
 
    program->config->float_mode = program->blocks[0].fp_mode.val;
diff --git a/src/amd/vulkan/radv_debug.c b/src/amd/vulkan/radv_debug.c
index 1bf604d2d86..b8a48fbcb49 100644
--- a/src/amd/vulkan/radv_debug.c
+++ b/src/amd/vulkan/radv_debug.c
@@ -978,6 +978,8 @@ radv_dump_faulty_shader(struct radv_device *device, uint64_t faulty_pc)
    free(instructions);
 }
 
+#define MAX_SGPRS 108
+
 struct radv_trap_handler_layout {
    uint32_t ttmp0;
    uint32_t ttmp1;
@@ -989,6 +991,8 @@ struct radv_trap_handler_layout {
       uint32_t gpr_alloc;
       uint32_t ib_sts;
    } sq_wave_regs;
+
+   uint32_t sgprs[MAX_SGPRS];
 };
 
 static void
@@ -1015,6 +1019,17 @@ radv_dump_sq_hw_regs(struct radv_device *device, const struct radv_trap_handler_
    fprintf(stderr, "\n\n");
 }
 
+static void
+radv_dump_sgprs(const struct radv_trap_handler_layout *layout)
+{
+   fprintf(stderr, "\nSGPRS:\n");
+   for (uint32_t i = 0; i < MAX_SGPRS; i += 4) {
+      fprintf(stderr, "s[%d-%d]={0x%08x, 0x%08x, 0x%08x, 0x%08x}\n", i, i + 3, layout->sgprs[i], layout->sgprs[i + 1],
+              layout->sgprs[i + 2], layout->sgprs[i + 3]);
+   }
+   fprintf(stderr, "\n\n");
+}
+
 void
 radv_check_trap_handler(struct radv_queue *queue)
 {
@@ -1040,6 +1055,7 @@ radv_check_trap_handler(struct radv_queue *queue)
 #endif
 
    radv_dump_sq_hw_regs(device, layout);
+   radv_dump_sgprs(layout);
 
    uint32_t ttmp0 = layout->ttmp0;
    uint32_t ttmp1 = layout->ttmp1;