From 81162265b1d7f976c3810b420754ff8403f3aa18 Mon Sep 17 00:00:00 2001
From: Rhys Perry <pendingchaos02@gmail.com>
Date: Wed, 19 May 2021 14:36:43 +0100
Subject: [PATCH] aco: do not clause NSA instructions
MIME-Version: 1.0
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According to LLVM, this has "unpredictable results on GFX10.1".

https://reviews.llvm.org/D102211

fossil-db (Navi10):
Totals from 26690 (17.81% of 149839) affected shaders:
CodeSize: 167935160 -> 167706280 (-0.14%); split: -0.14%, +0.00%
Instrs: 31801427 -> 31744142 (-0.18%); split: -0.18%, +0.00%
Latency: 732672435 -> 732622463 (-0.01%)
InvThroughput: 163361435 -> 163357838 (-0.00%); split: -0.00%, +0.00%
VClause: 546131 -> 546903 (+0.14%); split: -0.00%, +0.14%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Fixes: c353895c922 ("aco: use non-sequential addressing")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10898>
---
 src/amd/compiler/README-ISA.md             |  4 ++++
 src/amd/compiler/aco_form_hard_clauses.cpp | 14 +++++++++-----
 src/amd/compiler/tests/helpers.cpp         |  3 +++
 src/amd/compiler/tests/test_isel.cpp       |  2 +-
 4 files changed, 17 insertions(+), 6 deletions(-)

diff --git a/src/amd/compiler/README-ISA.md b/src/amd/compiler/README-ISA.md
index 678759ff25c..a790522ba4f 100644
--- a/src/amd/compiler/README-ISA.md
+++ b/src/amd/compiler/README-ISA.md
@@ -246,3 +246,7 @@ or vice versa: DS instruction, then a branch, then a VMEM/GLOBAL/SCRATCH instruc
 
 Mitigated by:
 Only `s_waitcnt_vscnt null, 0`. Needed even if the first instruction is a load.
+
+### NSAClauseBug
+
+"MIMG-NSA in a hard clause has unpredictable results on GFX10.1"
diff --git a/src/amd/compiler/aco_form_hard_clauses.cpp b/src/amd/compiler/aco_form_hard_clauses.cpp
index 13e9dfadc3d..223a4e2478a 100644
--- a/src/amd/compiler/aco_form_hard_clauses.cpp
+++ b/src/amd/compiler/aco_form_hard_clauses.cpp
@@ -73,14 +73,18 @@ void form_hard_clauses(Program *program)
          aco_ptr<Instruction>& instr = block.instructions[i];
 
          clause_type type = clause_other;
-         if (instr->isVMEM() && !instr->operands.empty())
+         if (instr->isVMEM() && !instr->operands.empty()) {
+            if (program->chip_class == GFX10 && instr->isMIMG() && get_mimg_nsa_dwords(instr.get()) > 0)
+               type = clause_other;
+            else
+               type = clause_vmem;
+         } else if (instr->isScratch() || instr->isGlobal()) {
             type = clause_vmem;
-         else if (instr->isScratch() || instr->isGlobal())
-            type = clause_vmem;
-         else if (instr->isFlat())
+         } else if (instr->isFlat()) {
             type = clause_flat;
-         else if (instr->isSMEM() && !instr->operands.empty())
+         } else if (instr->isSMEM() && !instr->operands.empty()) {
             type = clause_smem;
+         }
 
          if (type != current_type || num_instrs == 64 ||
              (num_instrs && !should_form_clause(current_instrs[0].get(), instr.get()))) {
diff --git a/src/amd/compiler/tests/helpers.cpp b/src/amd/compiler/tests/helpers.cpp
index 52f93e09ac4..7f3202fe3eb 100644
--- a/src/amd/compiler/tests/helpers.cpp
+++ b/src/amd/compiler/tests/helpers.cpp
@@ -265,6 +265,9 @@ VkDevice get_vk_device(enum chip_class chip_class)
    case GFX10:
       family = CHIP_NAVI10;
       break;
+   case GFX10_3:
+      family = CHIP_SIENNA_CICHLID;
+      break;
    default:
       family = CHIP_UNKNOWN;
       break;
diff --git a/src/amd/compiler/tests/test_isel.cpp b/src/amd/compiler/tests/test_isel.cpp
index 6434553eadf..a6aae159064 100644
--- a/src/amd/compiler/tests/test_isel.cpp
+++ b/src/amd/compiler/tests/test_isel.cpp
@@ -137,7 +137,7 @@ BEGIN_TEST(isel.gs.no_verts)
 END_TEST
 
 BEGIN_TEST(isel.sparse.clause)
-   for (unsigned i = GFX10; i <= GFX10; i++) {
+   for (unsigned i = GFX10_3; i <= GFX10_3; i++) {
       if (!set_variant((chip_class)i))
          continue;