nir: Rename Boolean-related opcodes to include 32 in the name
This is a squash of a bunch of individual changes:
nir/builder: Generate 32-bit bool opcodes transparently
nir/algebraic: Remap Boolean opcodes to the 32-bit variant
Use 32-bit opcodes in the NIR producers and optimizations
Generated with a little hand-editing and the following sed commands:
sed -i 's/nir_op_ball_fequal/nir_op_b32all_fequal/g' **/*.c
sed -i 's/nir_op_bany_fnequal/nir_op_b32any_fnequal/g' **/*.c
sed -i 's/nir_op_ball_iequal/nir_op_b32all_iequal/g' **/*.c
sed -i 's/nir_op_bany_inequal/nir_op_b32any_inequal/g' **/*.c
sed -i 's/nir_op_\([fiu]lt\)/nir_op_\132/g' **/*.c
sed -i 's/nir_op_\([fiu]ge\)/nir_op_\132/g' **/*.c
sed -i 's/nir_op_\([fiu]ne\)/nir_op_\132/g' **/*.c
sed -i 's/nir_op_\([fiu]eq\)/nir_op_\132/g' **/*.c
sed -i 's/nir_op_\([fi]\)ne32g/nir_op_\1neg/g' **/*.c
sed -i 's/nir_op_bcsel/nir_op_b32csel/g' **/*.c
Use 32-bit opcodes in the NIR back-ends
Generated with a little hand-editing and the following sed commands:
sed -i 's/nir_op_ball_fequal/nir_op_b32all_fequal/g' **/*.c
sed -i 's/nir_op_bany_fnequal/nir_op_b32any_fnequal/g' **/*.c
sed -i 's/nir_op_ball_iequal/nir_op_b32all_iequal/g' **/*.c
sed -i 's/nir_op_bany_inequal/nir_op_b32any_inequal/g' **/*.c
sed -i 's/nir_op_\([fiu]lt\)/nir_op_\132/g' **/*.c
sed -i 's/nir_op_\([fiu]ge\)/nir_op_\132/g' **/*.c
sed -i 's/nir_op_\([fiu]ne\)/nir_op_\132/g' **/*.c
sed -i 's/nir_op_\([fiu]eq\)/nir_op_\132/g' **/*.c
sed -i 's/nir_op_\([fi]\)ne32g/nir_op_\1neg/g' **/*.c
sed -i 's/nir_op_bcsel/nir_op_b32csel/g' **/*.c
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
committed by
Jason Ekstrand
parent
b569093566
commit
80e8dfe9de
@@ -27,6 +27,36 @@ template = """\
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#define _NIR_BUILDER_OPCODES_
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<%
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opcode_remap = {
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'flt' : 'flt32',
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'fge' : 'fge32',
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'feq' : 'feq32',
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'fne' : 'fne32',
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'ilt' : 'ilt32',
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'ige' : 'ige32',
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'ieq' : 'ieq32',
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'ine' : 'ine32',
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'ult' : 'ult32',
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'uge' : 'uge32',
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'ball_iequal2' : 'b32all_iequal2',
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'ball_iequal3' : 'b32all_iequal3',
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'ball_iequal4' : 'b32all_iequal4',
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'bany_inequal2' : 'b32any_inequal2',
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'bany_inequal3' : 'b32any_inequal3',
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'bany_inequal4' : 'b32any_inequal4',
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'ball_fequal2' : 'b32all_fequal2',
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'ball_fequal3' : 'b32all_fequal3',
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'ball_fequal4' : 'b32all_fequal4',
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'bany_fnequal2' : 'b32any_fnequal2',
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'bany_fnequal3' : 'b32any_fnequal3',
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'bany_fnequal4' : 'b32any_fnequal4',
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'bcsel' : 'b32csel',
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}
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opcode_remap32 = { op32 : op for op, op32 in opcode_remap.items() }
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def src_decl_list(num_srcs):
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return ', '.join('nir_ssa_def *src' + str(i) for i in range(num_srcs))
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@@ -35,8 +65,15 @@ def src_list(num_srcs):
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%>
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% for name, opcode in sorted(opcodes.items()):
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% if name in opcode_remap:
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<% continue %>
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% elif name in opcode_remap32:
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<% builder_name = opcode_remap32[name] %>
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% else:
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<% builder_name = name %>
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% endif
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static inline nir_ssa_def *
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nir_${name}(nir_builder *build, ${src_decl_list(opcode.num_inputs)})
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nir_${builder_name}(nir_builder *build, ${src_decl_list(opcode.num_inputs)})
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{
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return nir_build_alu(build, nir_op_${name}, ${src_list(opcode.num_inputs)});
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}
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