nir: Rename Boolean-related opcodes to include 32 in the name
This is a squash of a bunch of individual changes:
nir/builder: Generate 32-bit bool opcodes transparently
nir/algebraic: Remap Boolean opcodes to the 32-bit variant
Use 32-bit opcodes in the NIR producers and optimizations
Generated with a little hand-editing and the following sed commands:
sed -i 's/nir_op_ball_fequal/nir_op_b32all_fequal/g' **/*.c
sed -i 's/nir_op_bany_fnequal/nir_op_b32any_fnequal/g' **/*.c
sed -i 's/nir_op_ball_iequal/nir_op_b32all_iequal/g' **/*.c
sed -i 's/nir_op_bany_inequal/nir_op_b32any_inequal/g' **/*.c
sed -i 's/nir_op_\([fiu]lt\)/nir_op_\132/g' **/*.c
sed -i 's/nir_op_\([fiu]ge\)/nir_op_\132/g' **/*.c
sed -i 's/nir_op_\([fiu]ne\)/nir_op_\132/g' **/*.c
sed -i 's/nir_op_\([fiu]eq\)/nir_op_\132/g' **/*.c
sed -i 's/nir_op_\([fi]\)ne32g/nir_op_\1neg/g' **/*.c
sed -i 's/nir_op_bcsel/nir_op_b32csel/g' **/*.c
Use 32-bit opcodes in the NIR back-ends
Generated with a little hand-editing and the following sed commands:
sed -i 's/nir_op_ball_fequal/nir_op_b32all_fequal/g' **/*.c
sed -i 's/nir_op_bany_fnequal/nir_op_b32any_fnequal/g' **/*.c
sed -i 's/nir_op_ball_iequal/nir_op_b32all_iequal/g' **/*.c
sed -i 's/nir_op_bany_inequal/nir_op_b32any_inequal/g' **/*.c
sed -i 's/nir_op_\([fiu]lt\)/nir_op_\132/g' **/*.c
sed -i 's/nir_op_\([fiu]ge\)/nir_op_\132/g' **/*.c
sed -i 's/nir_op_\([fiu]ne\)/nir_op_\132/g' **/*.c
sed -i 's/nir_op_\([fiu]eq\)/nir_op_\132/g' **/*.c
sed -i 's/nir_op_\([fi]\)ne32g/nir_op_\1neg/g' **/*.c
sed -i 's/nir_op_bcsel/nir_op_b32csel/g' **/*.c
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
committed by
Jason Ekstrand
parent
b569093566
commit
80e8dfe9de
@@ -506,45 +506,45 @@ ntq_emit_comparison(struct v3d_compile *c, struct qreg *dest,
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bool cond_invert = false;
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switch (compare_instr->op) {
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case nir_op_feq:
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case nir_op_feq32:
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case nir_op_seq:
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vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHZ);
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break;
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case nir_op_ieq:
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case nir_op_ieq32:
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vir_PF(c, vir_XOR(c, src0, src1), V3D_QPU_PF_PUSHZ);
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break;
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case nir_op_fne:
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case nir_op_fne32:
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case nir_op_sne:
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vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHZ);
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cond_invert = true;
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break;
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case nir_op_ine:
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case nir_op_ine32:
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vir_PF(c, vir_XOR(c, src0, src1), V3D_QPU_PF_PUSHZ);
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cond_invert = true;
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break;
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case nir_op_fge:
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case nir_op_fge32:
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case nir_op_sge:
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vir_PF(c, vir_FCMP(c, src1, src0), V3D_QPU_PF_PUSHC);
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break;
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case nir_op_ige:
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case nir_op_ige32:
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vir_PF(c, vir_MIN(c, src1, src0), V3D_QPU_PF_PUSHC);
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cond_invert = true;
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break;
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case nir_op_uge:
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case nir_op_uge32:
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vir_PF(c, vir_SUB(c, src0, src1), V3D_QPU_PF_PUSHC);
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cond_invert = true;
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break;
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case nir_op_slt:
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case nir_op_flt:
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case nir_op_flt32:
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vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHN);
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break;
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case nir_op_ilt:
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case nir_op_ilt32:
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vir_PF(c, vir_MIN(c, src1, src0), V3D_QPU_PF_PUSHC);
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break;
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case nir_op_ult:
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case nir_op_ult32:
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vir_PF(c, vir_SUB(c, src0, src1), V3D_QPU_PF_PUSHC);
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break;
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@@ -565,7 +565,7 @@ ntq_emit_comparison(struct v3d_compile *c, struct qreg *dest,
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vir_uniform_f(c, 1.0), vir_uniform_f(c, 0.0));
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break;
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case nir_op_bcsel:
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case nir_op_b32csel:
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*dest = vir_SEL(c, cond,
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ntq_get_alu_src(c, sel_instr, 1),
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ntq_get_alu_src(c, sel_instr, 2));
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@@ -748,22 +748,22 @@ ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
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case nir_op_sne:
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case nir_op_sge:
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case nir_op_slt:
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case nir_op_feq:
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case nir_op_fne:
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case nir_op_fge:
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case nir_op_flt:
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case nir_op_ieq:
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case nir_op_ine:
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case nir_op_ige:
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case nir_op_uge:
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case nir_op_ilt:
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case nir_op_ult:
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case nir_op_feq32:
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case nir_op_fne32:
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case nir_op_fge32:
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case nir_op_flt32:
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case nir_op_ieq32:
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case nir_op_ine32:
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case nir_op_ige32:
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case nir_op_uge32:
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case nir_op_ilt32:
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case nir_op_ult32:
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if (!ntq_emit_comparison(c, &result, instr, instr)) {
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fprintf(stderr, "Bad comparison instruction\n");
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}
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break;
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case nir_op_bcsel:
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case nir_op_b32csel:
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result = ntq_emit_bcsel(c, instr, src);
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break;
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case nir_op_fcsel:
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