diff --git a/src/gallium/drivers/d3d12/ci/d3d12-quick_gl.txt b/src/gallium/drivers/d3d12/ci/d3d12-quick_gl.txt index 61c1d393f9f..38fbd26bb53 100644 --- a/src/gallium/drivers/d3d12/ci/d3d12-quick_gl.txt +++ b/src/gallium/drivers/d3d12/ci/d3d12-quick_gl.txt @@ -1508,7 +1508,6 @@ spec/arb_sparse_buffer/commit: skip spec/arb_sparse_buffer/minmax: skip spec/arb_stencil_texturing/draw: fail spec/arb_sync/clientwaitsync-timeout: skip -spec/arb_tessellation_shader/arb_tessellation_shader-tes-gs-max-output -small -scan 1 50: crash spec/arb_texture_barrier/arb_texture_barrier-blending-in-shader 32 1 1 128 1: skip spec/arb_texture_barrier/arb_texture_barrier-blending-in-shader 32 1 1 128 2: skip spec/arb_texture_barrier/arb_texture_barrier-blending-in-shader 32 1 1 128 3: skip @@ -3514,7 +3513,7 @@ summary: ---- -------- pass: 17873 fail: 2035 - crash: 12 + crash: 11 skip: 1445 timeout: 0 warn: 10 @@ -3524,4 +3523,4 @@ summary: changes: 0 fixes: 0 regressions: 0 - total: 21384 + total: 21383 diff --git a/src/gallium/drivers/d3d12/ci/gitlab-ci.yml b/src/gallium/drivers/d3d12/ci/gitlab-ci.yml index df1b43ebebe..fbde0b55b5c 100644 --- a/src/gallium/drivers/d3d12/ci/gitlab-ci.yml +++ b/src/gallium/drivers/d3d12/ci/gitlab-ci.yml @@ -32,7 +32,7 @@ test-d3d12-quick_gl: variables: PIGLIT_PROFILE: quick_gl PIGLIT_RESULTS: "d3d12-quick_gl" - PIGLIT_TESTS: -x nv_copy_depth_to_color -x glsl-1.30.execution.tex-miplevel-selection -x arb_timer_query.timestamp-get -x max-size -x query.gl_timestamp -x query.time-elapsed + PIGLIT_TESTS: -x nv_copy_depth_to_color -x glsl-1.30.execution.tex-miplevel-selection -x arb_timer_query.timestamp-get -x max-size -x query.gl_timestamp -x query.time-elapsed -x tes-gs-max-output test-d3d12-quick_shader: extends: diff --git a/src/microsoft/compiler/dxil_nir.c b/src/microsoft/compiler/dxil_nir.c index ff6a165dca2..9ce39df0404 100644 --- a/src/microsoft/compiler/dxil_nir.c +++ b/src/microsoft/compiler/dxil_nir.c @@ -2106,3 +2106,53 @@ dxil_nir_lower_discard_and_terminate(nir_shader *s) return nir_shader_instructions_pass(s, lower_kill, nir_metadata_none, NULL); } + +static bool +update_writes(struct nir_builder *b, nir_instr *instr, void *_state) +{ + if (instr->type != nir_instr_type_intrinsic) + return false; + nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr); + if (intr->intrinsic != nir_intrinsic_store_output) + return false; + + nir_io_semantics io = nir_intrinsic_io_semantics(intr); + if (io.location != VARYING_SLOT_POS) + return false; + + nir_ssa_def *src = intr->src[0].ssa; + unsigned write_mask = nir_intrinsic_write_mask(intr); + if (src->num_components == 4 && write_mask == 0xf) + return false; + + b->cursor = nir_before_instr(instr); + unsigned first_comp = nir_intrinsic_component(intr); + nir_ssa_def *channels[4] = { NULL, NULL, NULL, NULL }; + assert(first_comp + src->num_components <= ARRAY_SIZE(channels)); + for (unsigned i = 0; i < src->num_components; ++i) + if (write_mask & (1 << i)) + channels[i + first_comp] = nir_channel(b, src, i); + for (unsigned i = 0; i < 4; ++i) + if (!channels[i]) + channels[i] = nir_imm_intN_t(b, 0, src->bit_size); + + nir_instr_rewrite_src_ssa(instr, &intr->src[0], nir_vec(b, channels, 4)); + nir_intrinsic_set_component(intr, 0); + nir_intrinsic_set_write_mask(intr, 0xf); + return true; +} + +bool +dxil_nir_ensure_position_writes(nir_shader *s) +{ + if (s->info.stage != MESA_SHADER_VERTEX && + s->info.stage != MESA_SHADER_GEOMETRY && + s->info.stage != MESA_SHADER_TESS_EVAL) + return false; + if ((s->info.outputs_written & VARYING_BIT_POS) == 0) + return false; + + return nir_shader_instructions_pass(s, update_writes, + nir_metadata_block_index | nir_metadata_dominance, + NULL); +} diff --git a/src/microsoft/compiler/dxil_nir.h b/src/microsoft/compiler/dxil_nir.h index 9cee2f8fa78..9e31200f89b 100644 --- a/src/microsoft/compiler/dxil_nir.h +++ b/src/microsoft/compiler/dxil_nir.h @@ -76,6 +76,7 @@ bool dxil_nir_set_tcs_patches_in(nir_shader *nir, unsigned num_control_points); bool dxil_nir_lower_ubo_array_one_to_static(nir_shader *s); bool dxil_nir_fix_io_uint_type(nir_shader *s, uint64_t in_mask, uint64_t out_mask); bool dxil_nir_lower_discard_and_terminate(nir_shader* s); +bool dxil_nir_ensure_position_writes(nir_shader *s); #ifdef __cplusplus } diff --git a/src/microsoft/compiler/nir_to_dxil.c b/src/microsoft/compiler/nir_to_dxil.c index 3793ff81856..10f733ee7ea 100644 --- a/src/microsoft/compiler/nir_to_dxil.c +++ b/src/microsoft/compiler/nir_to_dxil.c @@ -3176,31 +3176,6 @@ emit_store_output_via_intrinsic(struct ntd_context *ctx, nir_intrinsic_instr *in } } - /* Make sure all SV_Position components are written, otherwise the DXIL - * validator complains. - */ - bool is_sv_pos = - ctx->mod.shader_kind != DXIL_COMPUTE_SHADER && - ctx->mod.shader_kind != DXIL_PIXEL_SHADER && - var->data.location == VARYING_SLOT_POS; - - if (is_sv_pos) { - const struct dxil_type *float_type = dxil_module_get_float_type(&ctx->mod, 32); - const struct dxil_value *float_undef = dxil_module_get_undef(&ctx->mod, float_type); - unsigned pos_wrmask = writemask << base_component; - - for (unsigned i = 0; i < 4; ++i) { - if (!(BITFIELD_BIT(i) & pos_wrmask)) { - const struct dxil_value *args[] = { - opcode, output_id, row, - dxil_module_get_int8_const(&ctx->mod, i), - float_undef, - }; - success &= dxil_emit_call_void(&ctx->mod, func, args, ARRAY_SIZE(args)); - } - } - } - return success; } @@ -5779,6 +5754,7 @@ nir_to_dxil(struct nir_shader *s, const struct nir_to_dxil_options *opts, NIR_PASS_V(s, nir_lower_frexp); NIR_PASS_V(s, nir_lower_flrp, 16 | 32 | 64, true); NIR_PASS_V(s, nir_lower_io, nir_var_shader_in | nir_var_shader_out, type_size_vec4, nir_lower_io_lower_64bit_to_32); + NIR_PASS_V(s, dxil_nir_ensure_position_writes); NIR_PASS_V(s, nir_lower_pack); NIR_PASS_V(s, dxil_nir_lower_system_values);